diff options
| author | Lu Baolu <baolu.lu@linux.intel.com> | 2025-11-20 15:25:24 +0800 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2025-11-20 11:35:15 +0100 |
| commit | 6cbc09b7719ec7fd9f650f18b3828b7f60c17881 (patch) | |
| tree | ecca0a8cb2422dc8715bad63600097cce78916d4 | |
| parent | c08934a61201db8f1d1c66fcc63fb2eb526b656d (diff) | |
iommu/vt-d: Restore previous domain::aperture_end calculation
Commit d373449d8e97 ("iommu/vt-d: Use the generic iommu page table")
changed the calculation of domain::aperture_end. Previously, it was
calculated as:
domain->domain.geometry.aperture_end =
__DOMAIN_MAX_ADDR(domain->gaw - 1);
where domain->gaw was limited to less than MGAW.
Currently, it is calculated purely based on the max level of the page
table that the hardware supports. This is incorrect as stated in Section
3.6 of the VT-d spec:
"Software using first-stage translation structures to translate an IO
Virtual Address (IOVA) must use canonical addresses. Additionally,
software must limit addresses to less than the minimum of MGAW and the
lower canonical address width implied by FSPM (i.e., 47-bit when FSPM
is 4-level and 56-bit when FSPM is 5-level)."
Restore the previous calculation method for domain::aperture_end to avoid
violating the spec. Incorrect aperture calculation causes GPU hangs
without generating VT-d faults on some Intel client platforms.
Fixes: d373449d8e97 ("iommu/vt-d: Use the generic iommu page table")
Reported-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Closes: https://lore.kernel.org/r/4f15cf3b-6fad-4cd8-87e5-6d86c0082673@intel.com
Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Suggested-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| -rw-r--r-- | drivers/iommu/intel/iommu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2d2f64ce2bc6..7b3016491ca5 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2817,6 +2817,16 @@ intel_iommu_domain_alloc_first_stage(struct device *dev, cfg.common.hw_max_vasz_lg2 = 57; else cfg.common.hw_max_vasz_lg2 = 48; + + /* + * Spec 3.6 First-Stage Translation: + * + * Software must limit addresses to less than the minimum of MGAW + * and the lower canonical address width implied by FSPM (i.e., + * 47-bit when FSPM is 4-level and 56-bit when FSPM is 5-level). + */ + cfg.common.hw_max_vasz_lg2 = min(cap_mgaw(iommu->cap), + cfg.common.hw_max_vasz_lg2); cfg.common.hw_max_oasz_lg2 = 52; cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE); |