diff options
| author | Sergey Matyukevich <geomatsi@gmail.com> | 2025-11-19 23:35:06 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@kernel.org> | 2025-11-22 09:19:42 +0800 |
| commit | 9f393d8e757f79060baf4b2e703bd6b2d0d8d323 (patch) | |
| tree | f0f93f566bd494c3201aa66290fc6ee91be44ebf | |
| parent | 3a8660878839faadb4f1a6dd72c3179c1df56787 (diff) | |
riscv: dts: allwinner: d1: fix vlenb property
According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.
[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
| -rw-r--r-- | arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 6367112e614a..a7442a508433 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -28,7 +28,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm", "xtheadvector"; - thead,vlenb = <128>; + thead,vlenb = <16>; #cooling-cells = <2>; cpu0_intc: interrupt-controller { |