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authorFong, Yan Kei <yan.kei.fong@altera.com>2025-09-11 09:58:11 +0800
committerDinh Nguyen <dinguyen@kernel.org>2025-10-14 22:07:20 -0500
commite928e15a3e97714356d6fcdbe7f7772c1c87d58a (patch)
tree5ca421f90cfa6ecabdbe37592708daeb5e53c842
parent76297a4a93c27f1fddd93e005e28371746c27387 (diff)
arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com> Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..9ee312bae8d2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -116,6 +116,8 @@
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";