diff options
| author | Wadim Egorov <w.egorov@phytec.de> | 2025-08-05 11:00:21 +0200 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2025-08-13 09:21:50 -0500 |
| commit | f13db4f77d54a6db644f09a168919ad1b3432f52 (patch) | |
| tree | ec6032c022c74495f3160a95a2d1a57822af0a57 | |
| parent | 6aa4c1a38cf10c9760f81d456b7f92ff157e5f83 (diff) | |
arm64: dts: ti: k3-am62a-phycore-som: Add 1.4GHz opp entry
The phyCORE-AM62Ax is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table
to enable this OPP
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250805090021.1407753-2-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 5dc5d2cb20cc..207ca00630d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -200,6 +200,15 @@ }; }; +&a53_opp_table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; +}; + &c7x_0 { mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; memory-region = <&c7x_0_dma_memory_region>, |