diff options
| author | Tao Zhang <quic_taozha@quicinc.com> | 2025-02-25 22:40:08 -0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-26 11:25:10 +0000 |
| commit | 0c0b6c05e208abc60ae0f1aab0660ab93b25cfc7 (patch) | |
| tree | 4ce46225c43eaef3af718acc204df223a2e1321f /Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm | |
| parent | 07f7c21745db0afa71a813e594f0983b8bd0f031 (diff) | |
coresight-tpdm: Add support to enable the lane for MCMB TPDM
Add the sysfs file to set/get the enablement of the lane. For MCMB
configurations, the field "E_LN" in CMB_CR register is the
individual lane enables. MCMB lane N is enabled for trace
generation when M_CMB_CR.E=1 and M_CMB_CR.E_LN[N]=1. For lanes
that are not implemented on a given MCMB configuration, the
corresponding bits of this field read as 0 and ignore writes.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-4-quic_jinlmao@quicinc.com
Diffstat (limited to 'Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 547540e330c6..a47ea46c6f9b 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -265,3 +265,10 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t Description: (RW) Set/Get which lane participates in the output pattern match cross trigger mechanism for the MCMB subunit TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select +Date: Feb 2025 +KernelVersion 6.15 +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com> +Description: + (RW) Set/Get the enablement of the individual lane. |