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authorTakashi Iwai <tiwai@suse.de>2025-12-01 16:25:31 +0100
committerTakashi Iwai <tiwai@suse.de>2025-12-01 16:25:31 +0100
commit72987d2ddc7e4d883d23be87eb858a003b81e2e0 (patch)
tree9d7120886e71d3ec864f8967e3f25c7bcae6bcd9 /arch/loongarch/include/asm/cpu.h
parentb72a6ddf6af225957d4b36f858d2a67b2e31fab6 (diff)
parent324f3e03e8a85931ce0880654e3c3eb38b0f0bba (diff)
Merge branch 'for-linus' into for-next
Pull remaining 6.18-devel changes. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'arch/loongarch/include/asm/cpu.h')
-rw-r--r--arch/loongarch/include/asm/cpu.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index dfb982fe8701..d4cd4041bee7 100644
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -101,7 +101,9 @@ enum cpu_type_enum {
#define CPU_FEATURE_HYPERVISOR 26 /* CPU has hypervisor (running in VM) */
#define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */
#define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */
-#define CPU_FEATURE_AVECINT 29 /* CPU has AVEC interrupt */
+#define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */
+#define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */
+#define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */
#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
@@ -132,6 +134,8 @@ enum cpu_type_enum {
#define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
#define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
#define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW)
+#define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT)
#define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT)
+#define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT)
#endif /* _ASM_CPU_H */