diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2024-01-03 17:16:03 -0600 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-01-08 10:39:12 +0100 |
| commit | 2f9060b1db4aa2c21c248e34476d8936a2b69cf6 (patch) | |
| tree | 666738efd029662d2e38b60c3fe3fd398c38376d /arch/mips/include/asm/sync.h | |
| parent | 8e1803900ef1b61ed33e6963d9e6a95028b41110 (diff) | |
MIPS: Fix typos
Fix typos, most reported by "codespell arch/mips". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-mips@vger.kernel.org
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/sync.h')
| -rw-r--r-- | arch/mips/include/asm/sync.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h index aabd097933fe..44c04a82d0b7 100644 --- a/arch/mips/include/asm/sync.h +++ b/arch/mips/include/asm/sync.h @@ -19,7 +19,7 @@ * * Ordering barriers can be more efficient than completion barriers, since: * - * a) Ordering barriers only require memory access instructions which preceed + * a) Ordering barriers only require memory access instructions which precede * them in program order (older instructions) to reach a point in the * load/store datapath beyond which reordering is not possible before * allowing memory access instructions which follow them (younger |