diff options
| author | Sahil Siddiq <sahilcdq0@gmail.com> | 2025-04-19 21:18:18 +0530 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2025-04-20 07:06:54 +0100 |
| commit | 0c4a6e79ef522554bc509294dfe69b24ee78205d (patch) | |
| tree | d7a3f8b1941033b1955794192a9e4a766c210075 /arch/openrisc/mm/init.c | |
| parent | efabefb05aa1fe534ddb1839980824a763a7f1b0 (diff) | |
openrisc: Introduce new utility functions to flush and invalidate caches
According to the OpenRISC architecture manual, the dcache and icache may
not be present. When these caches are present, the invalidate and flush
registers may be absent. The current implementation does not perform
checks to verify their presence before utilizing cache registers, or
invalidating and flushing cache blocks.
Introduce new functions to detect the presence of cache components and
related special-purpose registers.
There are a few places where a range of addresses have to be flushed or
invalidated and the implementation is duplicated. Introduce new utility
functions and macros that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/mm/init.c')
| -rw-r--r-- | arch/openrisc/mm/init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index d0cb1a0126f9..46b8720db08e 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -35,6 +35,7 @@ #include <asm/fixmap.h> #include <asm/tlbflush.h> #include <asm/sections.h> +#include <asm/cacheflush.h> int mem_init_done; @@ -176,8 +177,8 @@ void __init paging_init(void) barrier(); /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + local_icache_block_inv(0x900); + local_icache_block_inv(0xa00); /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by |