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| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2024-08-05 08:25:09 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2024-08-05 08:25:09 +0200 |
| commit | 2c25dcc2361949bc7da730d22de36c019c6bf1e3 (patch) | |
| tree | 3422f89adb17748bde8419918cb7959d79c773f3 /arch/parisc/include/asm/cache.h | |
| parent | ba5c778cab1dd3e4918f940989e771e2818afee8 (diff) | |
| parent | de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed (diff) | |
Merge tag 'v6.11-rc2' into media_stage
Linux 6.11-rc2
* tag 'v6.11-rc2': (283 commits)
Linux 6.11-rc2
profiling: remove profile=sleep support
arm: dts: arm: versatile-ab: Fix duplicate clock node name
runtime constants: deal with old decrepit linkers
clocksource: Fix brown-bag boolean thinko in cs_watchdog_read()
cifs: update internal version number
smb: client: fix FSCTL_GET_REPARSE_POINT against NetApp
smb3: add dynamic tracepoints for shutdown ioctl
cifs: Remove cifs_aio_ctx
smb: client: handle lack of FSCTL_GET_REPARSE_POINT support
arm64: jump_label: Ensure patched jump_labels are visible to all CPUs
syscalls: fix syscall macros for newfstat/newfstatat
uretprobe: change syscall number, again
thermal: core: Update thermal zone registration documentation
Revert "nouveau: rip out busy fence waits"
protect the fetch of ->fd[fd] in do_dup2() from mispredictions
x86/uaccess: Zero the 8-byte get_range case on failure on 32-bit
riscv: Fix linear mapping checks for non-contiguous memory regions
KVM: x86/mmu: fix determination of max NPT mapping level for private pages
PCI: pciehp: Retain Power Indicator bits for userspace indicators
...
Diffstat (limited to 'arch/parisc/include/asm/cache.h')
| -rw-r--r-- | arch/parisc/include/asm/cache.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 2a60d7a72f1f..a3f0f100f219 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -20,7 +20,16 @@ #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#ifdef CONFIG_PA20 +#define ARCH_DMA_MINALIGN 128 +#else +#define ARCH_DMA_MINALIGN 32 +#endif +#define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */ + +#define arch_slab_minalign() ((unsigned)dcache_stride) +#define cache_line_size() dcache_stride +#define dma_get_cache_alignment cache_line_size #define __read_mostly __section(".data..read_mostly") |