diff options
| author | Cyril Bur <cyrilbur@tenstorrent.com> | 2025-06-02 12:15:43 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2025-06-05 14:03:17 -0700 |
| commit | 265d6aba165c500389c80d394ac247460c443ef5 (patch) | |
| tree | 4c44f088d103b32e738be63f649b609e6bbdc3c8 /arch/riscv/include/asm/processor.h | |
| parent | 2670a39b1ea68fb0b9175e26e299f3fe974e0332 (diff) | |
riscv: uaccess: Only restore the CSR_STATUS SUM bit
During switch to csrs will OR the value of the register into the
corresponding csr. In this case we're only interested in restoring the
SUM bit not the entire register.
Signed-off-by: Cyril Bur <cyrilbur@tenstorrent.com>
Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorrent.com
Co-developed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 788aa64c01f1 ("riscv: save the SR_SUM status over switches")
Link: https://lore.kernel.org/r/20250602121543.1544278-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'arch/riscv/include/asm/processor.h')
| -rw-r--r-- | arch/riscv/include/asm/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 8111250f3c1b..24d3af4d3807 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -110,7 +110,7 @@ struct thread_struct { struct __riscv_d_ext_state fstate; unsigned long bad_cause; unsigned long envcfg; - unsigned long status; + unsigned long sum; u32 riscv_v_flags; u32 vstate_ctrl; struct __riscv_v_ext_state vstate; |