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authorThomas Gleixner <tglx@linutronix.de>2024-02-13 22:04:08 +0100
committerThomas Gleixner <tglx@linutronix.de>2024-02-15 22:07:37 +0100
commit22d63660c35eb751c63a709bf901a64c1726592a (patch)
treef395cefff3391d5ca00eaea95807477e398181f3 /arch/x86/kernel/cpu/topology_common.c
parent3d41009425225ca5e09016c634ecee513b4713bb (diff)
x86/cpu: Use common topology code for Intel
Intel CPUs use either topology leaf 0xb/0x1f evaluation or the legacy SMP/HT evaluation based on CPUID leaf 0x1/0x4. Move it over to the consolidated topology code and remove the random topology hacks which are sprinkled into the Intel and the common code. No functional change intended. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mhklinux@outlook.com> Tested-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Wang Wendy <wendy.wang@intel.com> Tested-by: K Prateek Nayak <kprateek.nayak@amd.com> Link: https://lore.kernel.org/r/20240212153624.893644349@linutronix.de
Diffstat (limited to 'arch/x86/kernel/cpu/topology_common.c')
-rw-r--r--arch/x86/kernel/cpu/topology_common.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index bcaaeecaf1a6..ef99499c9bbe 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -71,7 +71,6 @@ bool topo_is_converted(struct cpuinfo_x86 *c)
/* Temporary until everything is converted over. */
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
- case X86_VENDOR_INTEL:
case X86_VENDOR_HYGON:
return false;
default:
@@ -136,6 +135,10 @@ static void parse_topology(struct topo_scan *tscan, bool early)
case X86_VENDOR_ZHAOXIN:
parse_legacy(tscan);
break;
+ case X86_VENDOR_INTEL:
+ if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan))
+ parse_legacy(tscan);
+ break;
}
}