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authorAlex Deucher <alexander.deucher@amd.com>2025-04-13 10:16:58 -0400
committerAlex Deucher <alexander.deucher@amd.com>2025-04-21 10:54:56 -0400
commitac9984cee7e17fad030708f6462f272cf82a5f74 (patch)
tree662fd2ba2a8c0d1905ff2bf68feb1d5a05b14727 /drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
parent6b9d26089f56fb05c1f13027bfff53a63ba6f64d (diff)
drm/amdgpu/gfx11: properly reference EOP interrupts for userqs
Regardless of whether we disable kernel queues, we need to take an extra reference to the pipe interrupts for user queues to make sure they stay enabled in case we disable them for kernel queues. Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ac90f823e596..a528afe38e0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4832,10 +4832,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
bool enable)
{
- if (adev->gfx.disable_kq) {
- unsigned int irq_type;
- int m, p, r;
+ unsigned int irq_type;
+ int m, p, r;
+ if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
for (m = 0; m < adev->gfx.me.num_me; m++) {
for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
@@ -4849,7 +4849,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
return r;
}
}
+ }
+ if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
@@ -4866,6 +4868,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
}
}
}
+
return 0;
}