diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-11-06 17:20:47 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-11-07 20:29:43 +0200 |
| commit | 177deeea4db7fb1361c0846450a8bfb9814caece (patch) | |
| tree | 3b2744db34d6c3fceb056bd127fb7a9a7a6e113f /drivers/gpu/drm/i915/display/intel_lt_phy.c | |
| parent | d4270f090d90a3a5b974e7efdefeec2fe6a41232 (diff) | |
drm/i915/ltphy: Nuke bogus weird timeouts
The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
ways. Get rid of the weird fast timeouts, and just use the slow ones.
For consistency with intel_wait_for_register() we'll stick to the
default 2 usec fast timeout for all cases.
Someone really needs to properly document where all these magic numbers
came from...
This will let us eventually nuke intel_de_wait_custom() and convert
over to poll_timeout_us().
v2: Go for the longer (ms) timeout in case it actually matters
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_lt_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_lt_phy.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index ff5af9c25e6d..cd4ac9679fc9 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1178,8 +1178,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port), XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0), - XE3PLPD_MACCLK_TURNON_LATENCY_US, - XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL)) + 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL)) drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n", phy_name(phy)); @@ -1192,13 +1191,13 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_current_status, 0, - XE3PLPD_RESET_END_LATENCY_US, 2, NULL)) + 2, XE3PLPD_RESET_END_LATENCY_MS, NULL)) drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n", phy_name(phy)); if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, lane_phy_pulse_status, - XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL)) + 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL)) drm_warn(display->drm, "PHY %c PLL rate not changed\n", phy_name(phy)); @@ -1673,7 +1672,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port), XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0), - XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL)) + 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL)) drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n", phy_name(phy)); @@ -1701,7 +1700,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, lane_phy_pulse_status, - XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL)) + 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL)) drm_warn(display->drm, "PHY %c PLL rate not changed\n", phy_name(phy)); |