diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 08:54:54 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 09:03:49 +0530 |
| commit | fc9be0a10ca4ead8a738d98029be1c5313106453 (patch) | |
| tree | a310de7bfdab151e7d9ea528891fd0347b100592 /drivers/gpu/drm/i915/display/intel_lt_phy.c | |
| parent | 3a323c7e96507773733d77d4a898ea7dbd2c157e (diff) | |
drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
as the sequence remains unchanged when going from SNPS Phy to
LT Phy.
Bspec: 74495
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_lt_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_lt_phy.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index b6f71425cd19..239f7cdd373b 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -44,6 +44,13 @@ intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count) } static void +intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder, + u8 lane_mask, u8 state) +{ + intel_cx0_powerdown_change_sequence(encoder, lane_mask, state); +} + +static void intel_lt_phy_lane_reset(struct intel_encoder *encoder, u8 lane_count) { @@ -70,6 +77,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP); intel_lt_phy_setup_powerdown(encoder, lane_count); + intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, + XELPDP_P2_STATE_RESET); intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), XE3PLPD_MACCLK_RESET_0, 0); @@ -145,6 +154,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool lane_reversal = dig_port->lane_reversal; + u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); /* 1. Enable MacCLK at default 162 MHz frequency. */ intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); @@ -153,6 +163,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal); /* 3. Change owned PHY lanes power to Ready state. */ + intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, + XELPDP_P2_STATE_READY); + /* * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type, * encoded rate and encoded mode. |