diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2025-08-06 19:55:15 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-08-14 13:12:23 +0300 |
| commit | 7e757092373ccf147e23f46d1167718680db8ec6 (patch) | |
| tree | 50f78370ade79e464b13dfa337bcb63b935da6c8 /drivers/gpu/drm/i915/display/intel_overlay.c | |
| parent | 85cac9ff650dd6d20d7589c1577aeaa7ef62d944 (diff) | |
drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D
All the places that use DSPCLK_GATE_D are specific to certain platforms,
and the parametrization of it to support VLV/CHV MMIO display base isn't
really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D
and use it.
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/ac16d9d5192595944bf9bcf70aa721b504bc90c0.1754499175.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_overlay.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_overlay.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 159a5f998ea0..272f9e7af4d4 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -217,10 +217,9 @@ static void i830_overlay_clock_gating(struct intel_display *display, /* WA_OVERLAY_CLKGATE:alm */ if (enable) - intel_de_write(display, DSPCLK_GATE_D(display), 0); + intel_de_write(display, DSPCLK_GATE_D, 0); else - intel_de_write(display, DSPCLK_GATE_D(display), - OVRUNIT_CLOCK_GATE_DISABLE); + intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ pci_bus_read_config_byte(pdev->bus, |