Merge tag 'drm-next-2024-07-18' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "There's a lot of stuff in here, amd, i915 and xe have new platform
  work, lots of core rework around EDID handling, some new COMPILE_TEST
  options, maintainer changes and a lots of other stuff. Summary:

  core:
   - deprecate DRM data and return 0 date
   - connector: Create a set of helpers to help with HDMI support
   - Remove driver owner assignments
   - Allow more drivers to compile with COMPILE_TEST
   - Conversions to drm_edid
   - Sprinkle MODULE_DESCRIPTIONS everywhere they are missing
   - Remove drm_mm_replace_node
   - print: Add a drm prefix to warn level messages too, remove
            ___drm_dbg, consolidate prefix handling
   - New monochrome TV mode variant

  ttm:
   - improve number of page faults on some platforms
   - fix test builds under PREEMPT_RT
   - more test coverage

  ci:
   - Require a more recent version of mesa
   - improve farm setup and test generation

  dma-buf:
   - warn if reserving 0 fence slots
   - internal API heap enhancements

  fbdev:
   - Create memory manager optimized fbdev emulation

  panic:
   - Allow to select fonts
   - improve drm_fb_dma_get_scanout_buffer
   - Allow to dump kmsg to the screen

  bridge:
   - Remove redundant checks on bridge->encoder
   - Remove drm_bridge_chain_mode_fixup
   - bridge-connector: Plumb in the new HDMI helper
   - analogix_dp: Various improvements, handle AUX transfers timeout
   - samsung-dsim: Fix timings calculation
   - tc358767: Plenty of small fixes, fix no connector attach, fix
               clocks
   - sii902x: state validation improvements

  panels:
   - Switch panels from register table initialization to proper code
   - Now that the panel code tracks the panel state, remove every ad-hoc
     implementation in the panel drivers
   - More cleanup of prepare / enable state tracking in drivers
   - edp: Drop legacy panel compatibles
   - simple-bridge: Switch to devm_drm_bridge_add
   - New panels: Lincoln Tech Sol LCD185-101CT, Microtips Technology
                 13-101HIEBCAF0-C, Microtips Technology MF-103HIEB0GA0,
                 BOE nv110wum-l60, IVO t109nw41, WL-355608-A8, PrimeView
                 PM070WL4, Lincoln Technologies LCD197, Ortustech
                 COM35H3P70ULC, AUO G104STN01, K&d kd101ne3-40ti

  amdgpu:
   - DCN 4.0.x support
   - GC 12.0 support
   - GMC 12.0 support
   - SDMA 7.0 support
   - MES12 support
   - MMHUB 4.1 support
   - GFX12 modifier and DCC support
   - lots of IP fixes/updates

  amdkfd:
   - Contiguous VRAM allocations
   - GC 12.0 support
   - SDMA 7.0 support
   - SR-IOV fixes
   - KFD GFX ALU exceptions

  i915:
   - Battlemage Xe2 HPD display enablement
   - Panel Replay enabling
   - DP AUX-less ALPM/LOBF
   - Enable link training failure fallback for DP MST links
   - CMRR (Content Match Refresh Rate) enabling
   - Increase ADL-S/ADL-P/DG2+ max TMDS bitrate to 6 Gbps
   - Enable eDP AUX based HDR backlight
   - Support replaying GPU hangs with captured context image
   - Automate CCS Mode setting during engine resets
   - lots of refactoring
   - Support replaying GPU hangs with captured context image
   - Increase FLR timeout from 3s to 9s
   - Enable w/a 16021333562 for DG2, MTL and ARL [guc]

  xe:
   - update MAINATINERS
   - New uapi adding OA functionality to Xe
   - expose l3 bank mask
   - fix display detect on ADL-N
   - runtime PM Fixes
   - Fix silent backmerge issues
   - More prep for SR-IOV
   - HWmon additions
   - per client usage info
   - Rework GPU page fault handling
   - Drop EXEC_QUEUE_FLAG_BANNED
   - Add BMG PCI IDs
   - Scheduler fixes and improvements
   - Rename xe_exec_queue::compute to xe_exec_queue::lr
   - Use ttm_uncached for BO with NEEDS_UC flag
   - Rename xe perf layer as xe observation layer
   - lots of refactoring

  radeon:
   - Backlight workaround for iMac
   - Silence UBSAN flex array warnings

  msm:
   - Validate registers XML description against schema in CI
   - core/dpu: SM7150 support
   - mdp5: Add support for MSM8937
   - gpu: Add param for userspace to know if raytracing is supported
   - gpu: X185 support (aka gpu in X1 laptop chips)
   - gpu: a505 support

  ivpu:
   - hardware scheduler support
   - profiling support
   - improvements to the platform support layer
   - firmware handling improvements
   - clocks/power mgmt improvements
   - scheduler/logging improvements

  habanalabs:
   - Gradual sleep in polling memory macro
   - Reduce Gaudi2 MSI-X interrupt count to 128
   - Add Gaudi2-D revision support
   - Add timestamp to CPLD info
   - Gaudi2: Assume hard-reset by firmware upon MC SEI severe error
   - Align Gaudi2 interrupt names
   - Check for errors after preboot is ready
   - Change habanalabs maintainer and git repo path

  mgag200:
   - refactoring and improvements
   - Add BMC output
   - enable polling

  nouveau:
   - add registry command line

  v3d:
   - perf counters improvements

  zynqmp:
   - irq and debugfs improvements

  atmel-hlcdc:
   - Support XLCDC in sam9x7

  mipi-dbi:
   - Remove mipi_dbi_machine_little_endian
   - make SPI bits per word configurable
   - support RGB888
   - allow pixel formats to be specified in the DT

  sun4i:
   - Rework the blender setup for DE2

  panfrost:
   - Enable MT8188 support

  vc4:
   - Monochrome TV support

  exynos:
   - fix fallback mode regression
   - fix memory leak
   - Use drm_edid_duplicate() instead of kmemdup()

  etnaviv:
   - fix i.MX8MP NPU clock gating
   - workaround FE register cdc issues on some cores
   - fix DMA sync handling for cached buffers
   - fix job timeout handling
   - keep TS enabled on MMUv2 cores for improved performance

  mediatek:
   - Convert to platform remove callback returning void-
   - Drop chain_mode_fixup call in mode_valid()
   - Fixes the errors of MediaTek display driver found by IGT
   - Add display support for the MT8365-EVK board
   - Fix bit depth overwritten for mtk_ovl_set bit_depth()
   - Fix possible_crtcs calculation
   - Fix spurious kfree()

  ast:
   - refactor mode setting code

  stm:
   - Add LVDS support
   - DSI PHY updates"

* tag 'drm-next-2024-07-18' of https://gitlab.freedesktop.org/drm/kernel: (2501 commits)
  drm/amdgpu/mes12: add missing opcode string
  drm/amdgpu/mes11: update opcode strings
  Revert "drm/amd/display: Reset freesync config before update new state"
  drm/omap: Restrict compile testing to PAGE_SIZE less than 64KB
  drm/xe: Drop trace_xe_hw_fence_free
  drm/xe/uapi: Rename xe perf layer as xe observation layer
  drm/amdgpu: remove exp hw support check for gfx12
  drm/amdgpu: timely save bad pages to eeprom after gpu ras reset is completed
  drm/amdgpu: flush all cached ras bad pages to eeprom
  drm/amdgpu: select compute ME engines dynamically
  drm/amd/display: Allow display DCC for DCN401
  drm/amdgpu: select compute ME engines dynamically
  drm/amdgpu/job: Replace DRM_INFO/ERROR logging
  drm/amdgpu: select compute ME engines dynamically
  drm/amd/pm: Ignore initial value in smu response register
  drm/amdgpu: Initialize VF partition mode
  drm/amd/amdgpu: fix SDMA IRQ client ID <-> req mapping
  MAINTAINERS: fix Xinhui's name
  MAINTAINERS: update powerplay and swsmu
  drm/qxl: Pin buffer objects for internal mappings
  ...

1 files changed, 108 insertions, 110 deletions

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 31deda1c664a..1723f0e4faa4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -116,7 +116,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
 
 	tries = nb_tries;
 	while (tries--) {
-		val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
+		val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
 		pll_locked = !!(val & BIT(5));
 
 		if (pll_locked)
@@ -130,7 +130,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
 
 	tries = nb_tries;
 	while (tries--) {
-		val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
+		val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
 		pll_ready = !!(val & BIT(0));
 
 		if (pll_ready)
@@ -288,29 +288,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *p
 
 	data = pconf->ssc_adj_period;
 	data &= 0x0ff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1);
 	data = (pconf->ssc_adj_period >> 8);
 	data &= 0x03;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2);
 
 	data = pconf->ssc_period;
 	data &= 0x0ff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1);
 	data = (pconf->ssc_period >> 8);
 	data &= 0x0ff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2);
 
 	data = pconf->ssc_step_size;
 	data &= 0x0ff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1);
 	data = (pconf->ssc_step_size >> 8);
 	data &= 0x0ff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2);
 
 	data = (pconf->ssc_center & 0x01);
 	data <<= 1;
 	data |= 0x01; /* enable */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER);
 
 	wmb();	/* make sure register committed */
 }
@@ -323,43 +323,45 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
 
 	/* confgiure the non frequency dependent pll registers */
 	data = 0;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
+	writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */
+	writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL);
+	/* bandgap_timer */
+	writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2);
+	/* pll_wakeup_timer */
+	writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5);
 
 	data = pconf->pll_vco_div_ref & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1);
 	data = (pconf->pll_vco_div_ref >> 8) & 0x3;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2);
 
 	data = pconf->pll_kvco_div_ref & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1);
 	data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
+	writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
+	writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
+	writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
+	writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
+	writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
+	writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
+	writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
+	writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
+	writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
+	writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL);
 }
 
 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
@@ -369,13 +371,14 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
 	/* de assert pll start and apply pll sw reset */
 
 	/* stop pll */
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+	writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
 
 	/* pll sw reset */
-	dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
+	writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
+	udelay(10);
 	wmb();	/* make sure register committed */
 
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
+	writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
 	wmb();	/* make sure register committed */
 }
 
@@ -388,50 +391,50 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
 
 	DBG("DSI%d PLL", pll->phy->id);
 
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
+	writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
 
 	pll_db_commit_common(pll, pconf);
 
 	pll_14nm_software_reset(pll);
 
 	/* Use the /2 path in Mux */
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
+	writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1);
 
 	data = 0xff; /* data, clk, pll normal operation */
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
+	writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0);
 
 	/* configure the frequency dependent pll registers */
 	data = pconf->dec_start;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START);
 
 	data = pconf->div_frac_start & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1);
 	data = (pconf->div_frac_start >> 8) & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2);
 	data = (pconf->div_frac_start >> 16) & 0xf;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3);
 
 	data = pconf->plllock_cmp & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1);
 
 	data = (pconf->plllock_cmp >> 8) & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2);
 
 	data = (pconf->plllock_cmp >> 16) & 0x3;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3);
 
 	data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN);
 
 	data = pconf->pll_vco_count & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1);
 	data = (pconf->pll_vco_count >> 8) & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2);
 
 	data = pconf->pll_kvco_count & 0xff;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1);
 	data = (pconf->pll_kvco_count >> 8) & 0x3;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
+	writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2);
 
 	/*
 	 * High nibble configures the post divider internal to the VCO. It's
@@ -442,7 +445,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
 	 * 2: divided by 4
 	 * 3: divided by 8
 	 */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3);
+	writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV);
 
 	if (pconf->ssc_en)
 		pll_db_commit_ssc(pll, pconf);
@@ -497,16 +500,16 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
 	u32 dec_start;
 	u64 ref_clk = parent_rate;
 
-	dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
+	dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START);
 	dec_start &= 0x0ff;
 
 	DBG("dec_start = %x", dec_start);
 
-	div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
+	div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
 				& 0xf) << 16;
-	div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
+	div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
 				& 0xff) << 8;
-	div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
+	div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
 				& 0xff;
 
 	DBG("div_frac_start = %x", div_frac_start);
@@ -542,8 +545,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
 	if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
 		dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
+	writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1);
+	writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
 
 	locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
 					 POLL_TIMEOUT_US);
@@ -569,7 +572,7 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
 	if (unlikely(!pll_14nm->phy->pll_on))
 		return;
 
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+	writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
 
 	pll_14nm->phy->pll_on = false;
 }
@@ -611,7 +614,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
 
 	DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
 
-	val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
+	val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
 	val &= div_mask(width);
 
 	return divider_recalc_rate(hw, parent_rate, val, NULL,
@@ -653,11 +656,11 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	spin_lock_irqsave(lock, flags);
 
-	val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+	val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 	val &= ~(div_mask(width) << shift);
 
 	val |= value << shift;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
+	writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 
 	/* If we're master in bonded DSI mode, then the slave PLL's post-dividers
 	 * follow the master's post dividers
@@ -666,7 +669,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
 		void __iomem *slave_base = pll_14nm_slave->phy->base;
 
-		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
+		writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 	}
 
 	spin_unlock_irqrestore(lock, flags);
@@ -691,7 +694,7 @@ static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
 	void __iomem *cmn_base = pll_14nm->phy->base;
 	u32 data;
 
-	data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+	data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 
 	cached_state->n1postdiv = data & 0xf;
 	cached_state->n2postdiv = (data >> 4) & 0xf;
@@ -723,14 +726,14 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
 	DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
 	    cached_state->n1postdiv, cached_state->n2postdiv);
 
-	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
+	writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 
 	/* also restore post-dividers for slave DSI PLL */
 	if (phy->usecase == MSM_DSI_PHY_MASTER) {
 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
 		void __iomem *slave_base = pll_14nm_slave->phy->base;
 
-		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
+		writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 	}
 
 	return 0;
@@ -758,9 +761,9 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
 		return -EINVAL;
 	}
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
+	writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN);
 	if (bandgap)
-		dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
+		writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP);
 
 	return 0;
 }
@@ -917,27 +920,27 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
 	u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
 				   timing->hs_halfbyte_en;
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
-		      DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
-		      halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0);
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
-		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get));
-	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),
-		      DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx));
+	writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly),
+	       base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx));
+	writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0,
+	       base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
+	       DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx));
+	writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0),
+	       base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx));
 }
 
 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
@@ -961,49 +964,44 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
 	data = 0x1c;
 	if (phy->usecase != MSM_DSI_PHY_STANDALONE)
 		data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
+	writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
 
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1);
+	writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
 
 	/* 4 data lanes + 1 clk lane configuration */
 	for (i = 0; i < 5; i++) {
-		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i),
-			      0x1d);
-
-		dsi_phy_write(lane_base +
-			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff);
-		dsi_phy_write(lane_base +
-			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i),
-			      (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06);
-
-		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i),
-			      (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f);
-		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10);
-		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i),
-			      0);
-		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i),
-			      0x88);
+		writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i));
+
+		writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i));
+		writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06,
+		       lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i));
+
+		writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f,
+		       lane_base + REG_DSI_14nm_PHY_LN_CFG3(i));
+		writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i));
+		writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i));
+		writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i));
 
 		dsi_14nm_dphy_set_timing(phy, timing, i);
 	}
 
 	/* Make sure PLL is not start */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00);
+	writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
 
 	wmb(); /* make sure everything is written before reset and enable */
 
 	/* reset digital block */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80);
+	writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
 	wmb(); /* ensure reset is asserted */
 	udelay(100);
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
+	writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
 
-	glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+	glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
 	if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
 		glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
 	else
 		glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
+	writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
 	ret = dsi_14nm_set_usecase(phy);
 	if (ret) {
 		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
@@ -1012,15 +1010,15 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
 	}
 
 	/* Remove power down from PLL and all lanes */
-	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff);
+	writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0);
 
 	return 0;
 }
 
 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
 {
-	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0);
-	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0);
+	writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+	writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0);
 
 	/* ensure that the phy is completely disabled */
 	wmb();