diff options
| author | Joel Fernandes <joelagnelf@nvidia.com> | 2025-11-10 22:34:22 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2025-11-14 20:25:57 +0900 |
| commit | 945c1eee7dbeb0dcafc9d151eaa46a4273d386fa (patch) | |
| tree | 71dfb83f1a93e1d860a33c9aa099f201ca7438a6 /drivers/gpu/nova-core | |
| parent | bb58d1aee6081dba5f64eacf48993c077e99dd4a (diff) | |
gpu: nova-core: falcon: Add support to write firmware version
This will be needed by both the GSP boot code as well as GSP resume code
in the sequencer.
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-14-8ae4058e3c0e@nvidia.com>
Diffstat (limited to 'drivers/gpu/nova-core')
| -rw-r--r-- | drivers/gpu/nova-core/falcon.rs | 8 | ||||
| -rw-r--r-- | drivers/gpu/nova-core/regs.rs | 6 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 4c1f36073533..31904e1d804b 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -621,4 +621,12 @@ impl<E: FalconEngine + 'static> Falcon<E> { let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); cpuctl.active_stat() } + + /// Write the application version to the OS register. + #[expect(dead_code)] + pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) { + regs::NV_PFALCON_FALCON_OS::default() + .set_value(app_version) + .write(bar, &E::ID); + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 5d5ba766cd61..274e53a1a44d 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -230,6 +230,12 @@ register!(NV_PFALCON_FALCON_MAILBOX1 @ PFalconBase[0x00000044] { 31:0 value as u32; }); +// Used to store version information about the firmware running +// on the Falcon processor. +register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] { + 31:0 value as u32; +}); + register!(NV_PFALCON_FALCON_RM @ PFalconBase[0x00000084] { 31:0 value as u32; }); |