diff options
| author | Karol Kolacinski <karol.kolacinski@intel.com> | 2025-05-01 15:54:13 -0700 |
|---|---|---|
| committer | Tony Nguyen <anthony.l.nguyen@intel.com> | 2025-06-18 08:59:22 -0700 |
| commit | 1ff7a6c5d3f5d84a5036ef98bf8790de2ebd9360 (patch) | |
| tree | 36eb8256067c72b31c4148faeb618fe06f572af3 /drivers/net/ethernet/intel/ice/ice_common.c | |
| parent | be7f0c1f47c75315f4b0f16432104cdb7ba0773c (diff) | |
ice: rename TSPLL and CGU functions and definitions
Rename TSPLL and CGU functions, definitions etc. to match the file name
and have consistent naming scheme.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_common.c')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_common.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index 8cb3cb978ea1..bc292d61892c 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -2301,12 +2301,12 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); } else { - info->clk_freq = ICE_TIME_REF_FREQ_156_250; + info->clk_freq = ICE_TSPLL_FREQ_156_250; info->clk_src = ICE_CLK_SRC_TCXO; } - if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { - info->time_ref = (enum ice_time_ref_freq)info->clk_freq; + if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { + info->time_ref = (enum ice_tspll_freq)info->clk_freq; } else { /* Unknown clock frequency, so assume a (probably incorrect) * default to avoid out-of-bounds look ups of frequency @@ -2314,7 +2314,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, */ ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", info->clk_freq); - info->time_ref = ICE_TIME_REF_FREQ_25_000; + info->time_ref = ICE_TSPLL_FREQ_25_000; } ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", @@ -6134,17 +6134,17 @@ u32 ice_get_link_speed(u16 index) } /** - * ice_read_cgu_reg_e82x - Read a CGU register - * @hw: pointer to the HW struct + * ice_read_cgu_reg - Read a CGU register + * @hw: Pointer to the HW struct * @addr: Register address to read - * @val: storage for register value read + * @val: Storage for register value read * * Read the contents of a register of the Clock Generation Unit. Only - * applicable to E822 devices. + * applicable to E82X devices. * * Return: 0 on success, other error codes when failed to read from CGU. */ -int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) +int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) { struct ice_sbq_msg_input cgu_msg = { .opcode = ice_sbq_msg_rd, @@ -6166,17 +6166,17 @@ int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) } /** - * ice_write_cgu_reg_e82x - Write a CGU register - * @hw: pointer to the HW struct + * ice_write_cgu_reg - Write a CGU register + * @hw: Pointer to the HW struct * @addr: Register address to write - * @val: value to write into the register + * @val: Value to write into the register * * Write the specified value to a register of the Clock Generation Unit. Only - * applicable to E822 devices. + * applicable to E82X devices. * * Return: 0 on success, other error codes when failed to write to CGU. */ -int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) +int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) { struct ice_sbq_msg_input cgu_msg = { .opcode = ice_sbq_msg_wr, |