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authorBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:15:05 -0500
committerBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:15:05 -0500
commitdea140198b846f7432d78566b7b0b83979c72c2b (patch)
tree8b29188c91b6c6616d9aa391bdd2fc3c4fb4adb7 /drivers/pci/pci.c
parent63c83f1fff494068e1b9fdbd04814395eb2f72fd (diff)
parentf4e026f454d7bb6aa84901a37641132961054735 (diff)
Merge branch 'pci/misc'
- Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) - Fix typos and whitespace errors (Bjorn Helgaas) * pci/misc: PCI: Fix typos tools/Makefile: Remove pci target # Conflicts: # drivers/pci/endpoint/functions/pci-epf-test.c
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f12903df8ae0..4d7c9f64ea24 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4785,7 +4785,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
/*
* PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
- * after which we should expect an link active if the reset was
+ * after which we should expect the link to be active if the reset was
* successful. If so, software must wait a minimum 100ms before sending
* configuration requests to devices downstream this port.
*