Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "This release is almost entirely new drivers, with a couple of small
  changes in generic code.

  The biggest individual update is a rename of the existing Microchip
  driver and the addition of a new driver for the silicon SPI controller
  in their PolarFire SoCs. The overlap between the soft IP supported by
  the current driver and this new one is regrettably all in the IP and
  not in the register interface offered to software.

   - Add a time offset parameter for offloads, allowing them to be
     defined in relation to each other. This is useful for IIO type
     applcations where you trigger an operation then read the result
     after a delay.

   - Add a tracepoint for flash exec_ops, bringing the flash support
     more in line with the debuggability of vanilla SPI.

   - Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip
     PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm
     IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT
     K1 QuadSPI.

  There's also a small set of ASoC cleanups that I mistakenly applied to
  the SPI tree and then put more stuff on top of before it was brought
  to my attention, sorry about that"

* tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits)
  spi: microchip-core: Refactor FIFO read and write handlers
  spi: ch341: fix out-of-bounds memory access in ch341_transfer_one
  spi: microchip-core: Remove unneeded PM related macro
  spi: microchip-core: Use SPI_MODE_X_MASK
  spi: microchip-core: Utilise temporary variable for struct device
  spi: microchip-core: Replace dead code (-ENOMEM error message)
  spi: microchip-core: use min() instead of min_t()
  spi: dt-bindings: airoha: add compatible for EN7523
  spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: microchip: Enable compile-testing for FPGA SPI controllers
  spi: Fix potential uninitialized variable in probe()
  spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H
  spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
  spi: rzv2h-rspi: add support for loopback mode
  spi: rzv2h-rspi: add support for variable transfer clock
  spi: rzv2h-rspi: add support for using PCLK for transfer clock
  spi: rzv2h-rspi: make transfer clock rate finding chip-specific
  spi: rzv2h-rspi: avoid recomputing transfer frequency
  ...

1 files changed, 62 insertions, 2 deletions

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index a29934422356..21a14e800eed 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -9,6 +9,7 @@
 #include <linux/gpio/consumer.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
@@ -19,8 +20,6 @@
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
-#include <linux/platform_data/spi-davinci.h>
-
 #define CS_DEFAULT	0xFF
 
 #define SPIFMT_PHASE_MASK	BIT(16)
@@ -98,8 +97,69 @@
 #define SPIDEF		0x4c
 #define SPIFMT0		0x50
 
+#define SPI_IO_TYPE_POLL	1
+#define SPI_IO_TYPE_DMA		2
+
 #define DMA_MIN_BYTES	16
 
+enum {
+	SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+	SPI_VERSION_2, /* For DA8xx */
+};
+
+/**
+ * struct davinci_spi_platform_data - Platform data for SPI master device on DaVinci
+ *
+ * @version:	version of the SPI IP. Different DaVinci devices have slightly
+ *		varying versions of the same IP.
+ * @num_chipselect: number of chipselects supported by this SPI master
+ * @intr_line:	interrupt line used to connect the SPI IP to the ARM interrupt
+ *		controller withn the SoC. Possible values are 0 and 1.
+ * @prescaler_limit: max clock prescaler value
+ * @cshold_bug:	set this to true if the SPI controller on your chip requires
+ *		a write to CSHOLD bit in between transfers (like in DM355).
+ * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
+ *		device on the bus.
+ */
+struct davinci_spi_platform_data {
+	u8			version;
+	u8			num_chipselect;
+	u8			intr_line;
+	u8			prescaler_limit;
+	bool			cshold_bug;
+	enum dma_event_q	dma_event_q;
+};
+
+/**
+ * struct davinci_spi_config - Per-chip-select configuration for SPI slave devices
+ *
+ * @wdelay:	amount of delay between transmissions. Measured in number of
+ *		SPI module clocks.
+ * @odd_parity:	polarity of parity flag at the end of transmit data stream.
+ *		0 - odd parity, 1 - even parity.
+ * @parity_enable: enable transmission of parity at end of each transmit
+ *		data stream.
+ * @io_type:	type of IO transfer. Choose between polled, interrupt and DMA.
+ * @timer_disable: disable chip-select timers (setup and hold)
+ * @c2tdelay:	chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:	chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:	transmit data finished to SPI ENAn pin inactive time. Measured
+ *		in number of SPI clocks.
+ * @c2edelay:	chip-select active to SPI ENAn signal active time. Measured in
+ *		number of SPI clocks.
+ */
+struct davinci_spi_config {
+	u8	wdelay;
+	u8	odd_parity;
+	u8	parity_enable;
+	u8	io_type;
+	u8	timer_disable;
+	u8	c2tdelay;
+	u8	t2cdelay;
+	u8	t2edelay;
+	u8	c2edelay;
+};
+
 /* SPI Controller driver's private data. */
 struct davinci_spi {
 	struct spi_bitbang	bitbang;