Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi

Pull more SCSI updates from James Bottomley:
 "This is mostly fixes and cleanups and code reworks that trickled in
  across the merge window and the weeks leading up. The only substantive
  update is the Mediatek ufs driver which accounts for the bulk of the
  additions"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (37 commits)
  scsi: libsas: Use a bool for sas_deform_port() second argument
  scsi: libsas: Move declarations of internal functions to sas_internal.h
  scsi: libsas: Make sas_get_ata_info() static
  scsi: libsas: Simplify sas_ata_wait_eh()
  scsi: libsas: Refactor dev_is_sata()
  scsi: sd: Make sd shutdown issue START STOP UNIT appropriately
  scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
  scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes
  scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host
  scsi: ufs: ufs-mediatek: Add UFS host support for MT8195 SoC
  scsi: ufs: ufs-pci: Remove control of UIC Completion interrupt for Intel MTL
  scsi: ufs: core: Do not write interrupt enable register unnecessarily
  scsi: ufs: core: Set and clear UIC Completion interrupt as needed
  scsi: ufs: core: Remove duplicated code in ufshcd_send_bsg_uic_cmd()
  scsi: ufs: core: Move ufshcd_enable_intr() and ufshcd_disable_intr()
  scsi: ufs: ufs-pci: Remove UFS PCI driver's ->late_init() call back
  scsi: ufs: ufs-pci: Fix default runtime and system PM levels
  scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers
  scsi: ufs: host: mediatek: Support FDE (AES) clock scaling
  scsi: ufs: host: mediatek: Support clock scaling with Vcore binding
  ...

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 05d76a6bd772..e46dc5fa209d 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -133,6 +133,8 @@ enum ufs_mtk_host_caps {
 	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
 	/* Control MTCMOS with RTFF */
 	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,
+
+	UFS_MTK_CAP_MCQ_BROKEN_RTC             = 1 << 10,
 };
 
 struct ufs_mtk_crypt_cfg {
@@ -147,6 +149,11 @@ struct ufs_mtk_clk {
 	struct ufs_clk_info *ufs_sel_clki; /* Mux */
 	struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
 	struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
+	struct ufs_clk_info *ufs_fde_clki; /* Mux */
+	struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
+	struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
+	struct regulator *reg_vcore;
+	int vcore_volt;
 };
 
 struct ufs_mtk_hw_ver {
@@ -176,9 +183,11 @@ struct ufs_mtk_host {
 	bool mphy_powered_on;
 	bool unipro_lpm;
 	bool ref_clk_enabled;
+	bool clk_scale_up;
 	u16 ref_clk_ungating_wait_us;
 	u16 ref_clk_gating_wait_us;
 	u32 ip_ver;
+	bool legacy_ip_ver;
 
 	bool mcq_set_intr;
 	bool is_mcq_intr_enabled;
@@ -192,4 +201,27 @@ struct ufs_mtk_host {
 /* MTK RTT support number */
 #define MTK_MAX_NUM_RTT 2
 
+/* UFSHCI MTK ip version value */
+enum {
+	/* UFSHCI 3.1 */
+	IP_VER_MT6983    = 0x10360000,
+	IP_VER_MT6878    = 0x10420200,
+
+	/* UFSHCI 4.0 */
+	IP_VER_MT6897    = 0x10440000,
+	IP_VER_MT6989    = 0x10450000,
+	IP_VER_MT6899    = 0x10450100,
+	IP_VER_MT6991_A0 = 0x10460000,
+	IP_VER_MT6991_B0 = 0x10470000,
+	IP_VER_MT6993    = 0x10480000,
+
+	IP_VER_NONE      = 0xFFFFFFFF
+};
+
+enum ip_ver_legacy {
+	IP_LEGACY_VER_MT6781 = 0x10380000,
+	IP_LEGACY_VER_MT6879 = 0x10360000,
+	IP_LEGACY_VER_MT6893 = 0x20160706
+};
+
 #endif /* !_UFS_MEDIATEK_H */