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Diffstat (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi')
-rw-r--r--arch/arm64/boot/dts/exynos/google/gs101.dtsi315
1 files changed, 306 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 31c99526470d..d06d1d05f364 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/clock/google,gs101.h>
+#include <dt-bindings/clock/google,gs101-acpm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -72,80 +73,96 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0000>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0100>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0200>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0300>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
+ operating-points-v2 = <&cpucl0_opp_table>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0400>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
enable-method = "psci";
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0500>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
enable-method = "psci";
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
+ operating-points-v2 = <&cpucl1_opp_table>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-x1";
reg = <0x0600>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
enable-method = "psci";
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
+ operating-points-v2 = <&cpucl2_opp_table>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x1";
reg = <0x0700>;
+ clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
enable-method = "psci";
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
+ operating-points-v2 = <&cpucl2_opp_table>;
};
idle-states {
@@ -183,6 +200,273 @@
};
};
+ cpucl0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <537500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-574000000 {
+ opp-hz = /bits/ 64 <574000000>;
+ opp-microvolt = <600000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-738000000 {
+ opp-hz = /bits/ 64 <738000000>;
+ opp-microvolt = <618750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-930000000 {
+ opp-hz = /bits/ 64 <930000000>;
+ opp-microvolt = <668750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1098000000 {
+ opp-hz = /bits/ 64 <1098000000>;
+ opp-microvolt = <712500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1197000000 {
+ opp-hz = /bits/ 64 <1197000000>;
+ opp-microvolt = <731250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1328000000 {
+ opp-hz = /bits/ 64 <1328000000>;
+ opp-microvolt = <762500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1401000000 {
+ opp-hz = /bits/ 64 <1401000000>;
+ opp-microvolt = <781250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1598000000 {
+ opp-hz = /bits/ 64 <1598000000>;
+ opp-microvolt = <831250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <862500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1803000000 {
+ opp-hz = /bits/ 64 <1803000000>;
+ opp-microvolt = <906250>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
+ cpucl1_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <506250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-553000000 {
+ opp-hz = /bits/ 64 <553000000>;
+ opp-microvolt = <537500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-696000000 {
+ opp-hz = /bits/ 64 <696000000>;
+ opp-microvolt = <562500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-799000000 {
+ opp-hz = /bits/ 64 <799000000>;
+ opp-microvolt = <581250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <606250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1024000000 {
+ opp-hz = /bits/ 64 <1024000000>;
+ opp-microvolt = <625000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1197000000 {
+ opp-hz = /bits/ 64 <1197000000>;
+ opp-microvolt = <662500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1328000000 {
+ opp-hz = /bits/ 64 <1328000000>;
+ opp-microvolt = <687500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1491000000 {
+ opp-hz = /bits/ 64 <1491000000>;
+ opp-microvolt = <731250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1663000000 {
+ opp-hz = /bits/ 64 <1663000000>;
+ opp-microvolt = <775000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1836000000 {
+ opp-hz = /bits/ 64 <1836000000>;
+ opp-microvolt = <818750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1999000000 {
+ opp-hz = /bits/ 64 <1999000000>;
+ opp-microvolt = <868750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2130000000 {
+ opp-hz = /bits/ 64 <2130000000>;
+ opp-microvolt = <918750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2253000000 {
+ opp-hz = /bits/ 64 <2253000000>;
+ opp-microvolt = <968750>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
+ cpucl2_opp_table: opp-table-2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <500000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-851000000 {
+ opp-hz = /bits/ 64 <851000000>;
+ opp-microvolt = <556250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-984000000 {
+ opp-hz = /bits/ 64 <984000000>;
+ opp-microvolt = <575000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1106000000 {
+ opp-hz = /bits/ 64 <1106000000>;
+ opp-microvolt = <606250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1277000000 {
+ opp-hz = /bits/ 64 <1277000000>;
+ opp-microvolt = <631250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1426000000 {
+ opp-hz = /bits/ 64 <1426000000>;
+ opp-microvolt = <662500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1582000000 {
+ opp-hz = /bits/ 64 <1582000000>;
+ opp-microvolt = <693750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1745000000 {
+ opp-hz = /bits/ 64 <1745000000>;
+ opp-microvolt = <731250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-1826000000 {
+ opp-hz = /bits/ 64 <1826000000>;
+ opp-microvolt = <750000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2048000000 {
+ opp-hz = /bits/ 64 <2048000000>;
+ opp-microvolt = <793750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2188000000 {
+ opp-hz = /bits/ 64 <2188000000>;
+ opp-microvolt = <831250>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2252000000 {
+ opp-hz = /bits/ 64 <2252000000>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2401000000 {
+ opp-hz = /bits/ 64 <2401000000>;
+ opp-microvolt = <887500>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2507000000 {
+ opp-hz = /bits/ 64 <2507000000>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2630000000 {
+ opp-hz = /bits/ 64 <2630000000>;
+ opp-microvolt = <968750>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2704000000 {
+ opp-hz = /bits/ 64 <2704000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+
+ opp-2802000000 {
+ opp-hz = /bits/ 64 <2802000000>;
+ opp-microvolt = <1056250>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
/* ect node is required to be present by bootloader */
ect {
};
@@ -202,6 +486,7 @@
firmware {
acpm_ipc: power-management {
compatible = "google,gs101-acpm-ipc";
+ #clock-cells = <1>;
mboxes = <&ap2apm_mailbox>;
shmem = <&apm_sram>;
};
@@ -288,13 +573,19 @@
cmu_misc: clock-controller@10010000 {
compatible = "google,gs101-cmu-misc";
- reg = <0x10010000 0x8000>;
+ reg = <0x10010000 0x10000>;
#clock-cells = <1>;
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "bus", "sss";
};
+ sysreg_misc: syscon@10030000 {
+ compatible = "google,gs101-misc-sysreg", "syscon";
+ reg = <0x10030000 0x10000>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_SYSREG_MISC_PCLK>;
+ };
+
timer@10050000 {
compatible = "google,gs101-mct",
"samsung,exynos4210-mct";
@@ -365,7 +656,7 @@
cmu_peric0: clock-controller@10800000 {
compatible = "google,gs101-cmu-peric0";
- reg = <0x10800000 0x4000>;
+ reg = <0x10800000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>,
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
@@ -911,7 +1202,7 @@
cmu_peric1: clock-controller@10c00000 {
compatible = "google,gs101-cmu-peric1";
- reg = <0x10c00000 0x4000>;
+ reg = <0x10c00000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>,
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
@@ -1265,7 +1556,7 @@
cmu_hsi0: clock-controller@11000000 {
compatible = "google,gs101-cmu-hsi0";
- reg = <0x11000000 0x4000>;
+ reg = <0x11000000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>,
@@ -1277,6 +1568,12 @@
"usbdpdbg";
};
+ sysreg_hsi0: syscon@11020000 {
+ compatible = "google,gs101-hsi0-sysreg", "syscon";
+ reg = <0x11020000 0x10000>;
+ clocks = <&cmu_hsi0 CLK_GOUT_HSI0_SYSREG_HSI0_PCLK>;
+ };
+
usbdrd31_phy: phy@11100000 {
compatible = "google,gs101-usb31drd-phy";
reg = <0x11100000 0x0200>,
@@ -1332,7 +1629,7 @@
cmu_hsi2: clock-controller@14400000 {
compatible = "google,gs101-cmu-hsi2";
- reg = <0x14400000 0x4000>;
+ reg = <0x14400000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>,
<&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
@@ -1395,16 +1692,16 @@
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
- reg = <0x17400000 0x8000>;
+ reg = <0x17400000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";
};
- sysreg_apm: syscon@174204e0 {
+ sysreg_apm: syscon@17420000 {
compatible = "google,gs101-apm-sysreg", "syscon";
- reg = <0x174204e0 0x1000>;
+ reg = <0x17420000 0x10000>;
};
pmu_system_controller: system-controller@17460000 {
@@ -1497,7 +1794,7 @@
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
- reg = <0x1e080000 0x8000>;
+ reg = <0x1e080000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-08 18:16:45 +0000