diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 2bf867273ad0..b7706d0bc3aa 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -149,8 +149,78 @@ status = "okay"; }; +&mdio1_phy { + reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; +}; + +&mdio2_phy { + /* + * PHY2 Reset Configuration: + * + * SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2# + */ + reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>; +}; + &pinctrl { /* + * GMAC2 Pin Configuration: + * + * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 + * for Ethernet port 2 + */ + gmac2_pins: gmac2-pins { + pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */ + <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */ + <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */ + <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */ + <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */ + <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */ + <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */ + <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */ + <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */ + <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */ + <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */ + <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */ + <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */ + <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */ + <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */ + <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */ + <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */ + <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */ + <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */ + }; + + /* + * GMAC1 Pin Configuration: + * + * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and + * P35_0-P35_2 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */ + <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */ + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */ + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */ + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */ + <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */ + <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */ + <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */ + <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */ + <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */ + <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */ + <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */ + <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */ + <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */ + <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */ + <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */ + <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */ + <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */ + <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */ + }; + + /* * I2C0 Pin Configuration: * ------------------------ * Signal | Pin | SW6 @@ -182,3 +252,31 @@ <RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */ }; }; + +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; +}; |