diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3368.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3368.dtsi | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 73618df7a889..ce4b112b082b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -140,6 +140,12 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, @@ -847,6 +853,31 @@ status = "disabled"; }; + vop: vop@ff930000 { + compatible = "rockchip,rk3368-vop"; + reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + assigned-clock-rates = <400000000>, <200000000>; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3368_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + vop_mmu: iommu@ff930300 { compatible = "rockchip,iommu"; reg = <0x0 0xff930300 0x0 0x100>; @@ -858,6 +889,50 @@ status = "disabled"; }; + mipi_dsi: dsi@ff960000 { + compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x4000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&power RK3368_PD_VIO>; + resets = <&cru SRST_MIPIDSI0>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + mipi_out: port@1 { + reg = <1>; + }; + + }; + }; + + dphy: phy@ff968000 { + compatible = "rockchip,rk3368-dsi-dphy"; + reg = <0x0 0xff968000 0x0 0x4000>; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; + clock-names = "ref", "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_MIPIDPHYTX>; + reset-names = "apb"; + status = "disabled"; + }; + hevc_mmu: iommu@ff9a0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9a0440 0x0 0x40>, |