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path: root/drivers/gpu/drm/i915/display/intel_vrr.c
AgeCommit message (Expand)Author
2025-11-11drm/i915/de: Include units in intel_de_wait*() function namesVille Syrjälä
2025-10-25drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()Ville Syrjälä
2025-10-25drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() commentVille Syrjälä
2025-10-25drm/i915/vrr: Nuke intel_vrr_vmin_flipline()Ville Syrjälä
2025-10-25drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()Ville Syrjälä
2025-10-25drm/i915/vrr: s/crtc_state/old_crtc_state/ in intel_vrr_transcoder_disable()Ville Syrjälä
2025-10-25drm/i915/vrr: Move HAS_VRR() check into intel_vrr_set_transcoder_timings()Ville Syrjälä
2025-10-25drm/i915/vrr: Remove redundant HAS_VRR() checksVille Syrjälä
2025-10-25drm/i915/vrr: Always write TRANS_VRR_CTL in intel_vrr_set_transcoder_timings(...Ville Syrjälä
2025-10-25drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on always...Ville Syrjälä
2025-10-25drm/i915/vrr: Extract intel_vrr_tg_enable()Ville Syrjälä
2025-10-25drm/i915/vrr: Extract intel_vrr_tg_disable()Ville Syrjälä
2025-10-25drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()Ville Syrjälä
2025-10-25drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings()Ville Syrjälä
2025-10-25drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()Ville Syrjälä
2025-10-25drm/i915/vrr: Extract intel_vrr_set_vrr_timings()Ville Syrjälä
2025-10-25drm/i915/vrr: Move compute_fixed_rr_timings()Ville Syrjälä
2025-10-25drm/i195/vrr: Move crtc_state->vrr.{vmin,vmax} update into intel_vrr_compute_...Ville Syrjälä
2025-10-25drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bitVille Syrjälä
2025-10-25drm/i915/vrr: Compute fixed refresh rate timings the same way as CMRR timingsVille Syrjälä
2025-10-18drm/i915/vrr: Use optimized guardband whenever VRR TG is activeAnkit Nautiyal
2025-10-18drm/i915/vrr: Use the min static optimized guardbandAnkit Nautiyal
2025-10-16drm/i915/display: Add vblank_start adjustment logic for always-on VRR TGAnkit Nautiyal
2025-10-16drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardbandAnkit Nautiyal
2025-10-16drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/endAnkit Nautiyal
2025-09-25drm/i915/display: Drop intel_vrr_vblank_delay and use set_context_latencyAnkit Nautiyal
2025-09-25drm/i915/vrr: Clamp guardband as per hardware and timing constraintsAnkit Nautiyal
2025-09-25drm/i915/display: Wait for scl start instead of dsb_wait_vblanksAnkit Nautiyal
2025-09-25drm/i915/vrr: Use SCL for computing guardbandAnkit Nautiyal
2025-09-25drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay()Ankit Nautiyal
2025-09-24drm/i915/vrr: Refactor VRR live status wait into common helperAnkit Nautiyal
2025-09-20drm/i915/vrr: s/intel_vrr_flipline_offset/intel_vrr_vmin_flipline_offset/Ville Syrjälä
2025-09-20drm/i915/vrr: Hide the ICL/TGL intel_vrr_flipline_offset() mangling betterVille Syrjälä
2025-09-18drm/i915/vrr: Move the TGL SCL mangling of vmin/vmax/flipline deeperVille Syrjälä
2025-09-18drm/i915/vrr: Annotate some functions with "hw"Ville Syrjälä
2025-09-18drm/i915/vrr: Store guardband in crtc state even for icl/tglVille Syrjälä
2025-09-18drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full ...Ville Syrjälä
2025-06-11drm/i915/display: drop i915_reg.h include where possibleJani Nikula
2025-06-09drm/i915: split out display register macros to a separate fileJani Nikula
2025-05-19drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDPAnkit Nautiyal
2025-04-14drm/i915/vrr: Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwardsJouni Högander
2025-04-01drm/i915: reduce intel_wakeref.h dependenciesJani Nikula
2025-03-31drm/i915/display: Avoid use of VTOTAL.Vtotal bitsAnkit Nautiyal
2025-03-25drm/i915/vrr: Set trans_vrr_ctl in intel_vrr_set_transcoder_timings()Ankit Nautiyal
2025-03-25drm/i915/vrr: Always use VRR timing generator for PTL+Ankit Nautiyal
2025-03-25drm/i915/vrr: Allow fixed_rr with pipe joinerAnkit Nautiyal
2025-03-25drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset blockAnkit Nautiyal
2025-03-25drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr()Ankit Nautiyal
2025-03-25drm/i915/vrr: Use fixed timings for platforms that support VRRAnkit Nautiyal
2025-03-25drm/i915/display: Use fixed_rr timings in modeset sequenceAnkit Nautiyal
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-09 05:46:28 +0000