From be30c827e16e5527644f3126ceb050cb60301a0f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:30 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPCNTR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPCNTR register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/d9434a718658d7dc6dba1e8a54f80cd1503d0b33.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915/gvt/cmd_parser.c') diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 2c315caf2414..3b6529a6501b 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1315,7 +1315,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); if (info->plane == PLANE_A) { - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); } else if (info->plane == PLANE_B) { @@ -1381,7 +1381,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); -- cgit v1.2.3