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authorAlistair Popple <apopple@nvidia.com>2025-11-10 22:34:10 +0900
committerAlexandre Courbot <acourbot@nvidia.com>2025-11-14 11:05:58 +0900
commit1101c442410cd57af848c30804e985aab9e0e569 (patch)
tree0075563cbbaf5c5d70d847c02b8373a5e6599851
parent7c01dc25f5c828401a5807307c4f7dda6555469f (diff)
gpu: nova-core: Set correct DMA mask
Set the correct DMA mask. Without this DMA will fail on some setups. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-2-8ae4058e3c0e@nvidia.com>
-rw-r--r--drivers/gpu/nova-core/driver.rs16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver.rs
index 2509f75eccb9..d91bbc50cde7 100644
--- a/drivers/gpu/nova-core/driver.rs
+++ b/drivers/gpu/nova-core/driver.rs
@@ -4,6 +4,8 @@ use kernel::{
auxiliary,
c_str,
device::Core,
+ dma::Device,
+ dma::DmaMask,
pci,
pci::{
Class,
@@ -25,6 +27,15 @@ pub(crate) struct NovaCore {
}
const BAR0_SIZE: usize = SZ_16M;
+
+// For now we only support Ampere which can use up to 47-bit DMA addresses.
+//
+// TODO: Add an abstraction for this to support newer GPUs which may support
+// larger DMA addresses. Limiting these GPUs to smaller address widths won't
+// have any adverse affects, unless installed on systems which require larger
+// DMA addresses. These systems should be quite rare.
+const GPU_DMA_BITS: u32 = 47;
+
pub(crate) type Bar0 = pci::Bar<BAR0_SIZE>;
kernel::pci_device_table!(
@@ -62,6 +73,11 @@ impl pci::Driver for NovaCore {
pdev.enable_device_mem()?;
pdev.set_master();
+ // SAFETY: No concurrent DMA allocations or mappings can be made because
+ // the device is still being probed and therefore isn't being used by
+ // other threads of execution.
+ unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<GPU_DMA_BITS>())? };
+
let devres_bar = Arc::pin_init(
pdev.iomap_region_sized::<BAR0_SIZE>(0, c_str!("nova-core/bar0")),
GFP_KERNEL,