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authorThomas Gleixner <tglx@linutronix.de>2016-07-04 12:26:05 +0200
committerThomas Gleixner <tglx@linutronix.de>2016-07-04 12:26:05 +0200
commit8658be133baa92c06b6d832a436d437deb2e2a22 (patch)
tree8f798f4aae5892533831487e4838a85b95414a0f /arch/arc/mm/dma.c
parent4030103b9b2e060512f8292bb62582adfd02ebe8 (diff)
parent5e385a6ef31fbbf2acbda770aecc2bc2ff933d17 (diff)
Merge branch 'irq/for-block' into irq/core
Pull the irq affinity managing code which is in a seperate branch for block developers to pull.
Diffstat (limited to 'arch/arc/mm/dma.c')
-rw-r--r--arch/arc/mm/dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 8c8e36fa5659..73d7e4c75b7d 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -10,7 +10,7 @@
* DMA Coherent API Notes
*
* I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
- * implemented by accessintg it using a kernel virtual address, with
+ * implemented by accessing it using a kernel virtual address, with
* Cache bit off in the TLB entry.
*
* The default DMA address == Phy address which is 0x8000_0000 based.