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authorJesse Taube <jesse@rivosinc.com>2024-10-17 12:00:21 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2024-10-18 12:38:33 -0700
commitd1703dc7bc8ec7adb91f5ceaf1556ff1ed212858 (patch)
tree8d6cfe05cb0dc3aba319c9aea977598eaa7174bd /arch/riscv/kernel/vector.c
parentc05a62c92516d7679c819f8a5177cf84c8668954 (diff)
RISC-V: Detect unaligned vector accesses supported
Run an unaligned vector access to test if the system supports vector unaligned access. Add the result to a new key in hwprobe. This is useful for usermode to know if vector misaligned accesses are supported and if they are faster or slower than equivalent byte accesses. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-4-5b33500160f8@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel/vector.c')
-rw-r--r--arch/riscv/kernel/vector.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 682b3feee451..821818886fab 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -66,7 +66,7 @@ void __init riscv_v_setup_ctx_cache(void)
#endif
}
-static bool insn_is_vector(u32 insn_buf)
+bool insn_is_vector(u32 insn_buf)
{
u32 opcode = insn_buf & __INSN_OPCODE_MASK;
u32 width, csr;