diff options
| author | Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> | 2025-03-10 22:38:38 +0000 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 14:21:45 -0700 |
| commit | 36f257e3b0ba904f5a4e7fa8dafaa60e88cdd28c (patch) | |
| tree | 16639e4dbebf2772b1574fc8f8815aa2bab9cb07 /drivers/cxl/core/core.h | |
| parent | 315c2f0b53ba2645062627443a12cea73f3dad9c (diff) | |
acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors
When PCIe AER is in FW-First, OS should process CXL Protocol errors from
CPER records. Introduce support for handling and logging CXL Protocol
errors.
The defined trace events cxl_aer_uncorrectable_error and
cxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse them
to trace FW-First Protocol errors.
Since the CXL code is required to be called from process context and
GHES is in interrupt context, use workqueues for processing.
Similar to CXL CPER event handling, use kfifo to handle errors as it
simplifies queue processing by providing lock free fifo operations.
Add the ability for the CXL sub-system to register a workqueue to
process CXL CPER protocol errors.
[DJ: return cxl_cper_register_prot_err_work() directly in cxl_ras_init()]
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20250310223839.31342-2-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'drivers/cxl/core/core.h')
| -rw-r--r-- | drivers/cxl/core/core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 800466f96a68..c87dbfcc9403 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -115,4 +115,7 @@ bool cxl_need_node_perf_attrs_update(int nid); int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); +int cxl_ras_init(void); +void cxl_ras_exit(void); + #endif /* __CXL_CORE_H__ */ |