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authorMark Brown <broonie@kernel.org>2025-10-21 19:05:19 +0100
committerMark Brown <broonie@kernel.org>2025-10-21 19:05:19 +0100
commit2880c42a0de68e9eb979e5331fbd5b2c79e093ad (patch)
tree5d1637310889839165d9ae9594868c76a6c53808 /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
parentecba655bf54a661ffe078856cd8dbc898270e4b5 (diff)
parent6658472a3e2de08197acfe099ba71ee0e2505ecf (diff)
ASoC: amd: ps: Propagate the PCI subsystem Vendor and
Merge series from Simon Trimmer <simont@opensource.cirrus.com>: This series of two patches propagates the PCI subsystem Vendor and Device IDs so that they can be used by component drivers to differentiate firmware loads.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bff25ef3e2d0..61268aa82df4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -144,7 +144,8 @@ enum AMDGPU_DEBUG_MASK {
AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
AMDGPU_DEBUG_SMU_POOL = BIT(7),
AMDGPU_DEBUG_VM_USERPTR = BIT(8),
- AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9)
+ AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
+ AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)
};
unsigned int amdgpu_vram_limit = UINT_MAX;
@@ -2289,6 +2290,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)
pr_info("debug: disable kernel logs of correctable errors\n");
adev->debug_disable_ce_logs = true;
}
+
+ if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) {
+ pr_info("debug: allowing command submission to CE engine\n");
+ adev->debug_enable_ce_cs = true;
+ }
}
static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)