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authorTvrtko Ursulin <tvrtko.ursulin@intel.com>2022-02-25 13:44:44 +0000
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2022-02-25 13:44:44 +0000
commitdb927686e43ffebfc5d1693c1cb4fd74f462d99b (patch)
tree0cbd82aea0825efc1cb10bad4af664ed1bed9b83 /drivers/gpu/drm/i915/display/intel_overlay.c
parentb8986c889e7ac26c57cb548f8f344456fa925a2f (diff)
parent54f43c17d681f6d9523fcfaeefc9df77993802e1 (diff)
Merge drm/drm-next into drm-intel-gt-next
Matt needed some buddy allocator changes for landing DG2 small BAR support patches. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_overlay.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_overlay.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1a376e9a1ff3..76845d34ad0c 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
#include <drm/drm_fourcc.h>
+#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
@@ -38,6 +39,7 @@
#include "intel_display_types.h"
#include "intel_frontbuffer.h"
#include "intel_overlay.h"
+#include "intel_pci_config.h"
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
@@ -959,6 +961,9 @@ static int check_overlay_dst(struct intel_overlay *overlay,
const struct intel_crtc_state *pipe_config =
overlay->crtc->config;
+ if (rec->dst_height == 0 || rec->dst_width == 0)
+ return -EINVAL;
+
if (rec->dst_x < pipe_config->pipe_src_w &&
rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
rec->dst_y < pipe_config->pipe_src_h &&