diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-03-07 17:17:15 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-03-08 15:08:45 -0600 |
| commit | f4e026f454d7bb6aa84901a37641132961054735 (patch) | |
| tree | e6686eae2f068482c869a396664f14deeec6acc9 /drivers/pci/controller/pcie-altera.c | |
| parent | 86c2345aff3f5b48b53a73a15ffe6e0930e4170f (diff) | |
PCI: Fix typos
Fix typos and whitespace errors.
Link: https://lore.kernel.org/r/20250307231715.438518-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/controller/pcie-altera.c')
| -rw-r--r-- | drivers/pci/controller/pcie-altera.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c index eb55a7f8573a..e5b3d5dad4bc 100644 --- a/drivers/pci/controller/pcie-altera.c +++ b/drivers/pci/controller/pcie-altera.c @@ -149,7 +149,7 @@ static bool s10_altera_pcie_link_up(struct altera_pcie *pcie) * Altera PCIe port uses BAR0 of RC's configuration space as the translation * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space * using these registers, so it can be reached by DMA from EP devices. - * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt + * This BAR0 will also access to MSI vector when receiving MSI/MSI-X interrupt * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge * should be hidden during enumeration to avoid the sizing and resource * allocation by PCIe core. |