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| author | Thomas Gleixner <tglx@linutronix.de> | 2025-11-19 18:26:49 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2025-11-20 12:14:53 +0100 |
| commit | be4463fa2c7185823d2989562162d578b45a89ae (patch) | |
| tree | f0955daf833532d10d689eb1b3c092e8d3bd5462 /tools/testing/selftests/bpf/prog_tests/prog_array_init.c | |
| parent | 8cea569ca785060b8c5cc7800713ddc3b1548a94 (diff) | |
sched/mmcid: Cacheline align MM CID storage
Both the per CPU storage and the data in mm_struct are heavily used in
context switch. As they can end up next to other frequently modified data,
they are subject to false sharing.
Make them cache line aligned.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://patch.msgid.link/20251119172549.194111661@linutronix.de
Diffstat (limited to 'tools/testing/selftests/bpf/prog_tests/prog_array_init.c')
0 files changed, 0 insertions, 0 deletions