diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c09aa759f4d4..733ef4559131 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -35,7 +35,6 @@ #include <drm/drm_privacy_screen_consumer.h> #include "i915_reg.h" -#include "i915_utils.h" #include "icl_dsi.h" #include "intel_alpm.h" #include "intel_audio.h" @@ -53,6 +52,7 @@ #include "intel_display_power.h" #include "intel_display_regs.h" #include "intel_display_types.h" +#include "intel_display_utils.h" #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" #include "intel_dp.h" @@ -72,6 +72,7 @@ #include "intel_hotplug.h" #include "intel_hti.h" #include "intel_lspcon.h" +#include "intel_lt_phy.h" #include "intel_mg_phy_regs.h" #include "intel_modeset_lock.h" #include "intel_panel.h" @@ -1466,10 +1467,15 @@ static int translate_signal_level(struct intel_dp *intel_dp, u8 signal_levels) { struct intel_display *display = to_intel_display(intel_dp); + const u8 *signal_array; + size_t array_size; int i; - for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { - if (index_to_dp_signal_levels[i] == signal_levels) + signal_array = index_to_dp_signal_levels; + array_size = ARRAY_SIZE(index_to_dp_signal_levels); + + for (i = 0; i < array_size; i++) { + if (signal_array[i] == signal_levels) return i; } @@ -4240,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, &crtc_state->dpll_hw_state); } +static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); + + if (crtc_state->dpll_hw_state.ltpll.tbt_mode) + crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); + else + crtc_state->port_clock = + intel_lt_phy_calc_port_clock(encoder, crtc_state); + intel_ddi_get_config(encoder, crtc_state); +} + static void mtl_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -4559,6 +4578,13 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = conn_state->connector; u8 port_sync_transcoders = 0; + int ret = 0; + + if (intel_crtc_has_dp_encoder(crtc_state)) + ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); + + if (ret) + return ret; drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", encoder->base.base.id, encoder->base.name, @@ -5224,7 +5250,12 @@ void intel_ddi_init(struct intel_display *display, encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (DISPLAY_VER(display) >= 14) { + if (HAS_LT_PHY(display)) { + encoder->enable_clock = intel_xe3plpd_pll_enable; + encoder->disable_clock = intel_xe3plpd_pll_disable; + encoder->port_pll_type = intel_mtl_port_pll_type; + encoder->get_config = xe3plpd_ddi_get_config; + } else if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; @@ -5289,7 +5320,9 @@ void intel_ddi_init(struct intel_display *display, encoder->get_config = hsw_ddi_get_config; } - if (DISPLAY_VER(display) >= 14) { + if (HAS_LT_PHY(display)) { + encoder->set_signal_levels = intel_lt_phy_set_signal_levels; + } else if (DISPLAY_VER(display) >= 14) { encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; } else if (display->platform.dg2) { encoder->set_signal_levels = intel_snps_phy_set_signal_levels; |