summaryrefslogtreecommitdiff
path: root/drivers/mailbox
AgeCommit message (Collapse)Author
12 daysmailbox: th1520: fix clock imbalance on probe failureJohan Hovold
The purpose of the devm_add_action_or_reset() helper is to call the action function in case adding an action ever fails so drop the clock disable from the error path to avoid disabling the clocks twice. Fixes: 5d4d263e1c6b ("mailbox: Introduce support for T-head TH1520 Mailbox driver") Cc: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
12 daysmailbox: pcc: don't zero error registerJamie Iles
The error status mask for a type 3/4 subspace is used for reading the error status, and the bitwise inverse is used for clearing the error with the intent being to preserve any of the non-error bits. However, we were previously applying the mask to extract the status and then applying the inverse to the result which ended up clearing all bits. Instead, store the inverse mask in the preserve mask and then use that on the original value read from the error status so that only the error is cleared. Fixes: c45ded7e1135 ("mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)") Signed-off-by: Jamie Iles <jamie.iles@oss.qualcomm.com> Signed-off-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
12 daysmailbox: mtk-gpueb: Add missing 'static' to mailbox ops structNicolas Frattaroli
mtk_gpueb_mbox_ops should be declared static. However, due to its const nature, this specifier was missed, as it compiled fine without it and with no warning by the compiler. arc-linux-gcc (GCC) 12.5.0 doesn't seem to like it however, so add the static to fix that. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202510100629.3nGvrhEU-lkp@intel.com/ Fixes: dbca0eabb821 ("mailbox: add MediaTek GPUEB IPI mailbox") Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
12 daysmailbox: mtk-cmdq: Refine DMA address handling for the command bufferJason-JH Lin
GCE can only fetch the command buffer address from a 32-bit register. Some SoCs support a 35-bit command buffer address for GCE, which requires a right shift of 3 bits before setting the address into the 32-bit register. A comment has been added to the header of cmdq_get_shift_pa() to explain this requirement. To prevent the GCE command buffer address from being DMA mapped beyond its supported bit range, the DMA bit mask for the device is set during initialization. Additionally, to ensure the correct shift is applied when setting or reading the register that stores the GCE command buffer address, new APIs, cmdq_convert_gce_addr() and cmdq_revert_gce_addr(), have been introduced for consistent operations on this register. The variable type for the command buffer address has been standardized to dma_addr_t to prevent handling issues caused by type mismatches. Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform") Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
12 daysmailbox: mailbox-test: Fix debugfs_create_dir error checkingHaotian Zhang
The debugfs_create_dir() function returns ERR_PTR() on error, not NULL. The current null-check fails to catch errors. Use IS_ERR() to correctly check for errors. Fixes: 8ea4484d0c2b ("mailbox: Add generic mechanism for testing Mailbox Controllers") Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
12 daysmailbox: omap-mailbox: Check for pending msgs only when mbox is exclusiveBeleswar Padhi
On TI K3 devices, the mailbox resides in the Always-On power domain (LPSC_main_alwayson) and is shared among multiple processors. The mailbox is not solely exclusive to Linux. Currently, the suspend path checks all FIFO queues for pending messages and blocks suspend if any are present. This behavior is unnecessary for K3 devices, since some of the FIFOs are used for RTOS<->RTOS communication and are independent of Linux. For FIFOs used in Linux<->RTOS communication, any pending message would trigger an interrupt, which naturally prevents suspend from completing. Hence, there is no need for the mailbox driver to explicitly check for pending messages on K3 platforms. Introduce a device match flag to indicate whether the mailbox instance is exclusive to Linux, and skip the pending message check for non-exclusive instances (such as in K3). Fixes: a49f991e740f ("arm64: dts: ti: k3-am62-verdin: Add missing cfg for TI IPC Firmware") Closes: https://lore.kernel.org/all/sid7gtg5vay5qgicsl6smnzwg5mnneoa35cempt5ddwjvedaio@hzsgcx6oo74l/ Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Tested-by: Hiago De Franco <hiago.franco@toradex.com> Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-08Merge tag 'mailbox-v6.18' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox Pull mailbox updates from Jassi Brar: - Qualcomm: add Glymur CPUCP mailbox binding - Xilinx Zynq: misc cleanup - MediaTek: - add new GPUEB mailbox driver - cmdq: remove pm_runtime calls from send_data - gce: make clock-names optional - misc: - change mailbox-altera maintainer - remove redundant 'fast_io' in regmap_config - mhuv3: Remove no_free_ptr * tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: mtk-cmdq: Remove pm_runtime APIs from cmdq_mbox_send_data() mailbox: add MediaTek GPUEB IPI mailbox dt-bindings: mailbox: Add MT8196 GPUEB Mailbox mailbox: zynqmp-ipi: Fix SGI cleanup on unbind mailbox: zynqmp-ipi: Fix out-of-bounds access in mailbox cleanup loop mailbox: zynqmp-ipi: Remove dev.parent check in zynqmp_ipi_free_mboxes mailbox: zynqmp-ipi: Remove redundant mbox_controller_unregister() call mailbox: remove unneeded 'fast_io' parameter in regmap_config dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding MAINTAINERS: Change mailbox-altera maintainer mailbox: arm_mhuv3: Remove no_free_ptr() to maintain the original form of the pointer
2025-10-07mailbox: mtk-cmdq: Remove pm_runtime APIs from cmdq_mbox_send_data()Jason-JH Lin
pm_runtime_get_sync() and pm_runtime_put_autosuspend() were previously called in cmdq_mbox_send_data(), which is under a spinlock in msg_submit() (mailbox.c). This caused lockdep warnings such as "sleeping function called from invalid context" when running with lockdebug enabled. The BUG report: BUG: sleeping function called from invalid context at drivers/base/power/runtime.c:1164 in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 3616, name: kworker/u17:3 preempt_count: 1, expected: 0 RCU nest depth: 0, expected: 0 INFO: lockdep is turned off. irq event stamp: 0 CPU: 1 PID: 3616 Comm: kworker/u17:3 Not tainted 6.1.87-lockdep-14133-g26e933aca785 #1 Hardware name: Google Ciri sku0/unprovisioned board (DT) Workqueue: imgsys_runner imgsys_runner_func Call trace: dump_backtrace+0x100/0x120 show_stack+0x20/0x2c dump_stack_lvl+0x84/0xb4 dump_stack+0x18/0x48 __might_resched+0x354/0x4c0 __might_sleep+0x98/0xe4 __pm_runtime_resume+0x70/0x124 cmdq_mbox_send_data+0xe4/0xb1c msg_submit+0x194/0x2dc mbox_send_message+0x190/0x330 imgsys_cmdq_sendtask+0x1618/0x2224 imgsys_runner_func+0xac/0x11c process_one_work+0x638/0xf84 worker_thread+0x808/0xcd0 kthread+0x24c/0x324 ret_from_fork+0x10/0x20 Additionally, pm_runtime_put_autosuspend() should be invoked from the GCE IRQ handler to ensure the hardware has actually completed its work. To resolve these issues, remove the pm_runtime calls from cmdq_mbox_send_data() and delegate power management responsibilities to the client driver. Fixes: 8afe816b0c99 ("mailbox: mtk-cmdq-mailbox: Implement Runtime PM with autosuspend") Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: add MediaTek GPUEB IPI mailboxNicolas Frattaroli
The MT8196 SoC uses an embedded MCU to control frequencies and power of the GPU. This controller is referred to as "GPUEB". It communicates to the application processor, among other ways, through a mailbox. The mailbox exposes one interrupt, which appears to only be fired when a response is received, rather than a transaction is completed. For us, this means we unfortunately need to poll for txdone. The mailbox also requires the EB clock to be on when touching any of the mailbox registers. Add a simple driver for it based on the common mailbox framework. Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: zynqmp-ipi: Fix SGI cleanup on unbindHarini T
The driver incorrectly determines SGI vs SPI interrupts by checking IRQ number < 16, which fails with dynamic IRQ allocation. During unbind, this causes improper SGI cleanup leading to kernel crash. Add explicit irq_type field to pdata for reliable identification of SGI interrupts (type-2) and only clean up SGI resources when appropriate. Fixes: 6ffb1635341b ("mailbox: zynqmp: handle SGI for shared IPI") Signed-off-by: Harini T <harini.t@amd.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: zynqmp-ipi: Fix out-of-bounds access in mailbox cleanup loopHarini T
The cleanup loop was starting at the wrong array index, causing out-of-bounds access. Start the loop at the correct index for zero-indexed arrays to prevent accessing memory beyond the allocated array bounds. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Harini T <harini.t@amd.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: zynqmp-ipi: Remove dev.parent check in zynqmp_ipi_free_mboxesHarini T
The ipi_mbox->dev.parent check is unreliable proxy for registration status as it fails to protect against probe failures that occur after the parent is assigned but before device_register() completes. device_is_registered() is the canonical and robust method to verify the registration status. Remove ipi_mbox->dev.parent check in zynqmp_ipi_free_mboxes(). Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Harini T <harini.t@amd.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: zynqmp-ipi: Remove redundant mbox_controller_unregister() callHarini T
The controller is registered using the device-managed function 'devm_mbox_controller_register()'. As documented in mailbox.c, this ensures the devres framework automatically calls mbox_controller_unregister() when device_unregister() is invoked, making the explicit call unnecessary. Remove redundant mbox_controller_unregister() call as device_unregister() handles controller cleanup. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Harini T <harini.t@amd.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: remove unneeded 'fast_io' parameter in regmap_configWolfram Sang
When using MMIO with regmap, fast_io is implied. No need to set it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-10-06mailbox: arm_mhuv3: Remove no_free_ptr() to maintain the original form of ↵Liao Yuanhong
the pointer Remove no_free_ptr() to ensure PTR_ERR() consistently retrieves the correct error code. Signed-off-by: Liao Yuanhong <liaoyuanhong@vivo.com> Acked-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-09-25mailbox/riscv-sbi-mpxy: Add ACPI supportSunil V L
Add ACPI support for the RISC-V SBI message proxy (MPXY) based mailbox driver. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-22-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-09-24mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driverAnup Patel
Add a mailbox controller driver for the new SBI message proxy extension which is part of the SBI v3.0 specification. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-8-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-09-24mailbox: Allow controller specific mapping using fwnodeAnup Patel
Introduce optional fw_node() callback which allows a mailbox controller driver to provide controller specific mapping using fwnode. The Linux OF framework already implements fwnode operations for the Linux DD framework so the fw_xlate() callback works fine with device tree as well. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-6-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-08-07mailbox/pcc: support mailbox management of the shared bufferAdam Young
Define a new, optional, callback that allows the driver to specify how the return data buffer is allocated. If that callback is set, mailbox/pcc.c is now responsible for reading from and writing to the PCC shared buffer. This also allows for proper checks of the Commnand complete flag between the PCC sender and receiver. For Type 4 channels, initialize the command complete flag prior to accepting messages. Since the mailbox does not know what memory allocation scheme to use for response messages, the client now has an optional callback that allows it to allocate the buffer for a response message. When an outbound message is written to the buffer, the mailbox checks for the flag indicating the client wants an tx complete notification via IRQ. Upon receipt of the interrupt It will pair it with the outgoing message. The expected use is to free the kernel memory buffer for the previous outgoing message. Signed-off-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: bcm74110: Fix spelling mistakeColin Ian King
There is a spelling mistake in the author's email address. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Reviewed-by: Justin Chen <justin.chen@broadcom.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: bcm74110: remove unneeded semicolonJiapeng Chong
No functional modification involved. ./drivers/mailbox/bcm74110-mailbox.c:483:2-3: Unneeded semicolon. ./drivers/mailbox/bcm74110-mailbox.c:563:2-3: Unneeded semicolon. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=22936 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: aspeed: add mailbox driver for AST27XX series SoCJammy Huang
Add mailbox controller driver for AST27XX SoCs, which provides independent tx/rx mailbox between different processors. There are 4 channels for each tx/rx mailbox and each channel has an 32-byte FIFO. Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: Add support for bcm74110Justin Chen
The bcm74110 mailbox driver is used to communicate with a co-processor for various power management and firmware related tasks. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: Use dev_fwnode()Jiri Slaby (SUSE)
irq_domain_create_simple() takes fwnode as the first argument. It can be extracted from the struct device using dev_fwnode() helper instead of using of_node with of_fwnode_handle(). So use the dev_fwnode() helper. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-08-06mailbox: mtk-cmdq: Switch to pm_runtime_put_autosuspend()Sakari Ailus
__pm_runtime_put_autosuspend() was meant to be used by callers that needed to put the Runtime PM usage_count without marking the device's last busy timestamp. It was however seen that the Runtime PM autosuspend related functions should include that call. Thus switch the driver to use pm_runtime_put_autosuspend(). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-07-21Merge branch 'newsoc/cix-p1' into soc/newsocArnd Bergmann
Patches from Peter Chen <peter.chen@cixtech.com>: Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview Currently, to run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs. https://docs.radxa.com/en/orion/o6/bios/install-bios In this series, we add initial SoC and board support for Kernel building. Since mailbox is used for SCMI clock communication, mailbox driver is added in this series for the minimum SoC support. Patch 1-2: add dt-binding doc for CIX and its sky1 SoC Patch 3: add Arm64 build support Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol. Patch 6: add Arm64 defconfig support Patch 7-8: add initial dts support for SoC and Orion O6 board Patch 9: add MAINTAINERS entry * newsoc/cix-p1: MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver dt-bindings: mailbox: add cix,sky1-mbox arm64: Kconfig: add ARCH_CIX for cix silicons dt-bindings: arm: add CIX P1 (SKY1) SoC dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21mailbox: add CIX mailbox driverGuomin Chen
The CIX mailbox controller, used in the Cix SoCs, like sky1. facilitates message transmission between multiple processors within the SoC, such as the AP, PM, audio DSP, SensorHub MCU, and others. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Lihua Liu <Lihua.Liu@cixtech.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-06-08treewide, timers: Rename from_timer() to timer_container_of()Ingo Molnar
Move this API to the canonical timer_*() namespace. [ tglx: Redone against pre rc1 ] Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/aB2X0jCKQO56WdMt@gmail.com
2025-06-02Merge tag 'mailbox-v6.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox Pull mailbox updates from Jassi Brar: "Core: - misc cleanup sophgo: - add driver for CV18XX series qcom: - add SM7150 APCS compatible - apcs: added separate clock node imx: - fix tx doorbell send microchip: - misc compile option fix mediatek: - Refine GCE_GCTL_VALUE setting" * tag 'mailbox-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: qcom-apcs-ipc: Assign OF node to clock controller child device dt-bindings: mailbox: qcom,apcs: Add separate node for clock-controller dt-bindings: mailbox: qcom: Add the SM7150 APCS compatible mailbox: sophgo: add mailbox driver for CV18XX series SoC dt-bindings: mailbox: add Sophgo CV18XX series SoC mailbox: Use guard/scoped_guard for spinlock mailbox: Use guard/scoped_guard for con_mutex mailbox: Remove devm_mbox_controller_unregister mailbox: Propagate correct error return value mailbox: Not protect module_put with spin_lock_irqsave mailbox: Use dev_err when there is error mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting mailbox: imx: Fix TXDB_V2 sending mailbox: mchp-ipc-sbi: Fix COMPILE_TEST build error
2025-05-29mailbox: qcom-apcs-ipc: Assign OF node to clock controller child deviceStephan Gerhold
Currently, the child device for the clock controller inside the APCS block is created without any OF node assigned, so the drivers need to rely on the parent device for obtaining any resources. Add support for defining the clock controller inside a "clock-controller" subnode to break up circular dependencies between the mailbox and required parent clocks of the clock controller. For backwards compatibility, if the subnode is not defined, reuse the OF node from the parent device. Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: sophgo: add mailbox driver for CV18XX series SoCYuntao Dai
Add mailbox controller driver for CV18XX SoCs, which provides 8 channels and each channel has an 8-byte FIFO. Signed-off-by: Yuntao Dai <d1581209858@live.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Use guard/scoped_guard for spinlockPeng Fan
Use guard and scoped_guard for chan->lock and mbox->poll_hrt_lock to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Use guard/scoped_guard for con_mutexPeng Fan
Use guard and scoped_guard for con_mutex to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Remove devm_mbox_controller_unregisterPeng Fan
Commit e898d9cdd3a9("mailbox: Add device-managed registration functions") introduced device-managed API for mailbox, but in the past 7 years, there is no user for devm_mbox_controller_unregister. So remove it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Propagate correct error return valuePeng Fan
In case of_property_match_string fails, it makes more sense to return its error value to caller, not force the value to ERR_PTR(-EINVAL). Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Not protect module_put with spin_lock_irqsavePeng Fan
&chan->lock is not supposed to protect 'chan->mbox'. And in __mbox_bind_client, try_module_get is also not protected by &chan->lock. So move module_put out of the lock protected region. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: Use dev_err when there is errorPeng Fan
Use dev_err to show the error log instead of using dev_dbg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE settingJason-JH Lin
Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and GCE_DDR_EN together in the same GCE_GCTL_VALUE register. For the SoCs whose GCE is located in MMINFRA and uses MMINFRA_AO power, this allows it to be written without enabling the clocks. Otherwise, all GCE registers should be written after the GCE clocks are enabled. Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend() to ensure it is called when the GCE clock is enabled. Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support flow") Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: imx: Fix TXDB_V2 sendingPeng Fan
i.MX95 features several processing domains, Cortex-M7, Cortex-A55 secure, Cortex-A55 non-secure. Each domain could communicate with SCMI firmware with a dedicated MU. But the current NXP SCMI firmware is not a RTOS, all processing logic codes are in interrupt context. So if high priority Cortex-M7 is communicating with SCMI firmware and requires a bit more time to handle the SCMI call, Linux MU TXDB_V2 will be timeout with high possiblity in 1000us(the current value in imx-mailbox.c). Per NXP SCMI firmware design, if timeout, there is no recover logic, so SCMI agents should never timeout and always wait until the check condition met. Based on the upper reason, enlarge the timeout value to 10ms which is less chance to timeout, and retry if timeout really happends. Fixes: 5bfe4067d350 ("mailbox: imx: support channel type tx doorbell v2") Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-26mailbox: mchp-ipc-sbi: Fix COMPILE_TEST build errorYue Haibing
If COMPILE_TEST is y but RISCV_SBI is n, build fails: drivers/mailbox/mailbox-mchp-ipc-sbi.c: In function 'mchp_ipc_sbi_chan_send': drivers/mailbox/mailbox-mchp-ipc-sbi.c:119:23: error: storage size of 'ret' isn't known struct sbiret ret; ^~~ CC drivers/nvmem/lpc18xx_otp.o drivers/mailbox/mailbox-mchp-ipc-sbi.c:121:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration] ret = sbi_ecall(SBI_EXT_MICROCHIP_TECHNOLOGY, command, channel, ^~~~~~~~~ move COMPILE_TEST to ARCH_MICROCHIP dependency as other drivers. Fixes: e4b1d67e7141 ("mailbox: add Microchip IPC support") Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-05-16mailbox: qcom-ipcc: Switch to irq_domain_create_tree()Jiri Slaby (SUSE)
irq_domain_add_tree() is going away as being obsolete now. Switch to the preferred irq_domain_create_tree(). That differs in the first parameter: It takes more generic struct fwnode_handle instead of struct device_node. Therefore, of_fwnode_handle() is added around the parameter. Note some of the users can likely use dev->fwnode directly instead of indirect of_fwnode_handle(dev->of_node). But dev->fwnode is not guaranteed to be set for all, so this has to be investigated on case to case basis (by people who can actually test with the HW). [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-23-jirislaby@kernel.org
2025-04-05treewide: Switch/rename to timer_delete[_sync]()Thomas Gleixner
timer_delete[_sync]() replaces del_timer[_sync](). Convert the whole tree over and remove the historical wrapper inlines. Conversion was done with coccinelle plus manual fixups where necessary. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-03-29Merge tag 'mailbox-v6.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox Pull mailbox updates from Jassi Brar: "Core: - misc rejig of header includes - minor const fixes Misc: - constify amba_id table pcc: - cleanup and refactoring of shmem and irq handling qcom: - add MSM8226 compatible fsl,mu: - add i.MX94 compatible mediatek: - remove cl in struct cmdq_pkt tegra: - define dimensioning masks in SoC data" * tag 'mailbox-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: (25 commits) mailbox: Remove unneeded semicolon mailbox: pcc: Refactor and simplify check_and_ack() mailbox: pcc: Always map the shared memory communication address mailbox: pcc: Refactor error handling in irq handler into separate function mailbox: pcc: Use acpi_os_ioremap() instead of ioremap() mailbox: pcc: Return early if no GAS register from pcc_mbox_cmd_complete_check mailbox: pcc: Drop unnecessary endianness conversion of pcc_hdr.flags mailbox: pcc: Always clear the platform ack interrupt first mailbox: pcc: Fix the possible race in updation of chan_in_use flag dt-bindings: mailbox: qcom: add compatible for MSM8226 SoC dt-bindings: mailbox: fsl,mu: Add i.MX94 compatible MAINTAINERS: add mailbox API's tree type and location mailbox: remove unused header files mailbox: explicitly include <linux/bits.h> mailbox: sort headers alphabetically mailbox: don't protect of_parse_phandle_with_args with con_mutex mailbox: use error ret code of of_parse_phandle_with_args() mailbox: arm_mhuv2: Constify amba_id table mailbox: arm_mhu_db: Constify amba_id table mailbox: arm_mhu: Constify amba_id table ...
2025-03-26mailbox: Remove unneeded semicolonChen Ni
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the semantic patch at scripts/coccinelle/misc/semicolon.cocci. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Refactor and simplify check_and_ack()Sudeep Holla
The existing check_and_ack() function had unnecessary complexity. The logic could be streamlined to improve code readability and maintainability. The command update register needs to be updated in order to acknowledge the platform notification through type 4 channel. So it can be done unconditionally. Currently it is complicated just to make use of pcc_send_data() which also executes the same updation. In order to simplify, let us just ring the doorbell directly from check_and_ack() instead of calling into pcc_send_data(). While at it, rename it into pcc_chan_check_and_ack() to maintain consistency in the driver. Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Always map the shared memory communication addressSudeep Holla
Currently the shared memory communication address was mapped by the mailbox client drivers leading to all sorts of inconsistencies. It also has resulted in the inconsistent attributes used while mapping the shared memory regions. In order to remove/eliminate any issues, let us ensures the shared memory address is always mapped and unmapped when the PCC channels are requested and release. We need to map them as the ACPI PCCT associates these shared memory with each channel subspace and may need use the status or the flags in the headers of those shared memory communication address regions to manage the transport/channel. Note, until all the drivers using PCC start using this mapped shmem, there might be double mapping of the shared memory address. This shouldn't have any impact on existing mbox client drivers. Since there are no users of pcc_chan_ioremap() and also it is mapped by default, we can stop exporting it and merge the functionality into pcc_mbox_request_channel(). Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Refactor error handling in irq handler into separate functionSudeep Holla
The existing error handling logic in pcc_mbox_irq() is intermixed with the main flow of the function. The command complete check and the complete complete update/acknowledgment are nicely factored into separate functions. Moves error detection and clearing logic into a separate function called: pcc_mbox_error_check_and_clear() by extracting error-handling logic from pcc_mbox_irq(). This ensures error checking and clearing are handled separately and it improves maintainability by keeping the IRQ handler focused on processing events. Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Use acpi_os_ioremap() instead of ioremap()Sudeep Holla
The Platform Communication Channel (PCC) mailbox driver currently uses ioremap() to map channel shared memory regions. However it is preferred to use acpi_os_ioremap(), which is mapping function specific to EFI/ACPI defined memory regions. It ensures that the correct memory attributes are applied when mapping ACPI-provided regions. While at it, also add checks for handling any errors with the mapping. Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Return early if no GAS register from pcc_mbox_cmd_complete_checkSudeep Holla
pcc_mbox_cmd_complete_check() accesses pchan->cmd_complete.gas to check command completion status. Even if GAS is NULL, pcc_chan_reg_read() gets called which returns success doing nothing and then we return. Add an early return if pchan->cmd_complete.gas == NULL before performing any operations. Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2025-03-26mailbox: pcc: Drop unnecessary endianness conversion of pcc_hdr.flagsSudeep Holla
The Sparse static checker flags a type mismatch warning related to endianness conversion: | warning: incorrect type in argument 1 (different base types) | expected restricted __le32 const [usertype] *p | got unsigned int * This is because an explicit endianness conversion (le32_to_cpu()) was applied unnecessarily to a pcc_hdr.flags field that is already in little-endian format. The PCC driver is only enabled on little-endian kernels due to its dependency on ACPI and EFI, making the explicit conversion unnecessary. The redundant conversion occurs in pcc_chan_check_and_ack() for the pcc_hdr.flags field. Drop this unnecessary endianness conversion of pcc_hdr.flags. Also drop the redundant PCC_ACK_FLAG_MASK definition and use the more appropriate and already defined PCC_CMD_COMPLETION_NOTIFY. Acked-by: Huisong Li <lihuisong@huawei.com> Tested-by: Adam Young <admiyo@os.amperecomputing.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-10 19:34:29 +0000