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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "bst,c1200";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x100>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x200>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x300>;
enable-method = "psci";
next-level-cache = <&l2_cache>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
uart0: serial@20008000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x20008000 0x0 0x1000>;
clock-frequency = <25000000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
gic: interrupt-controller@32800000 {
compatible = "arm,gic-v3";
reg = <0x0 0x32800000 0x0 0x10000>,
<0x0 0x32880000 0x0 0x100000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
timer {
compatible = "arm,armv8-timer";
always-on;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
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