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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright 2025 Tenstorrent AI ULC
/dts-v1/;
/ {
compatible = "tenstorrent,blackhole";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <50000000>;
cpu@0 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <0>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@1 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <1>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@2 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <2>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@3 {
compatible = "sifive,x280", "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <3>;
mmu-type = "riscv,sv57";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
clint0: timer@2000000 {
compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
<&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
<&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
<&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
};
plic0: interrupt-controller@c000000 {
compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
reg = <0x0 0x0c000000 0x0 0x04000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <0>;
riscv,ndev = <128>;
};
};
};
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