1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
|
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G3E System controller (SYS) driver
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include "rz-sysc.h"
/* Register Offsets */
#define SYS_LSI_MODE 0x300
/*
* BOOTPLLCA[1:0]
* [0,0] => 1.1GHZ
* [0,1] => 1.5GHZ
* [1,0] => 1.6GHZ
* [1,1] => 1.7GHZ
*/
#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
#define SYS_LSI_PRR 0x308
#define SYS_LSI_PRR_CA55_DIS BIT(8)
#define SYS_LSI_PRR_NPU_DIS BIT(1)
#define SYS_LSI_OTPTSU1TRMVAL0 0x330
#define SYS_LSI_OTPTSU1TRMVAL1 0x334
#define SYS_SPI_STAADDCS0 0x900
#define SYS_SPI_ENDADDCS0 0x904
#define SYS_SPI_STAADDCS1 0x908
#define SYS_SPI_ENDADDCS1 0x90c
#define SYS_VSP_CLK 0xe00
#define SYS_GBETH0_CFG 0xf00
#define SYS_GBETH1_CFG 0xf04
#define SYS_PCIE_INTX_CH0 0x1000
#define SYS_PCIE_MSI1_CH0 0x1004
#define SYS_PCIE_MSI2_CH0 0x1008
#define SYS_PCIE_MSI3_CH0 0x100c
#define SYS_PCIE_MSI4_CH0 0x1010
#define SYS_PCIE_MSI5_CH0 0x1014
#define SYS_PCIE_PME_CH0 0x1018
#define SYS_PCIE_ACK_CH0 0x101c
#define SYS_PCIE_MISC_CH0 0x1020
#define SYS_PCIE_MODE_CH0 0x1024
#define SYS_ADC_CFG 0x1600
static void rzg3e_sys_print_id(struct device *dev,
void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr)
{
bool is_quad_core, npu_enabled;
u32 prr_val, mode_val;
prr_val = readl(sysc_base + SYS_LSI_PRR);
mode_val = readl(sysc_base + SYS_LSI_MODE);
/* Check CPU and NPU configuration */
is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
is_quad_core ? "Quad" : "Dual", soc_dev_attr->family,
soc_dev_attr->soc_id, soc_dev_attr->revision,
npu_enabled ? " with Ethos-U55" : "");
/* Check CA55 PLL configuration */
if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
}
static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = {
.family = "RZ/G3E",
.id = 0x8679447,
.devid_offset = 0x304,
.revision_mask = GENMASK(31, 28),
.specific_id_mask = GENMASK(27, 0),
.print_id = rzg3e_sys_print_id,
};
static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_LSI_OTPTSU1TRMVAL0:
case SYS_LSI_OTPTSU1TRMVAL1:
case SYS_SPI_STAADDCS0:
case SYS_SPI_ENDADDCS0:
case SYS_SPI_STAADDCS1:
case SYS_SPI_ENDADDCS1:
case SYS_VSP_CLK:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SYS_SPI_STAADDCS0:
case SYS_SPI_ENDADDCS0:
case SYS_SPI_STAADDCS1:
case SYS_SPI_ENDADDCS1:
case SYS_VSP_CLK:
case SYS_GBETH0_CFG:
case SYS_GBETH1_CFG:
case SYS_PCIE_INTX_CH0:
case SYS_PCIE_MSI1_CH0:
case SYS_PCIE_MSI2_CH0:
case SYS_PCIE_MSI3_CH0:
case SYS_PCIE_MSI4_CH0:
case SYS_PCIE_MSI5_CH0:
case SYS_PCIE_PME_CH0:
case SYS_PCIE_ACK_CH0:
case SYS_PCIE_MISC_CH0:
case SYS_PCIE_MODE_CH0:
case SYS_ADC_CFG:
return true;
default:
return false;
}
}
const struct rz_sysc_init_data rzg3e_sys_init_data = {
.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
.readable_reg = rzg3e_regmap_readable_reg,
.writeable_reg = rzg3e_regmap_writeable_reg,
.max_register = 0x170c,
};
|
