diff options
| author | Maxime Ripard <mripard@kernel.org> | 2025-08-27 17:12:43 +0200 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> | 2025-09-01 10:37:19 +0300 |
| commit | 68f7fa24776e2821896dd95ba0cf1a77a302575f (patch) | |
| tree | 33d1384b7d3736740603cf3bacb3815fc8ad80a7 /drivers/gpu/drm/tidss | |
| parent | b695ff1e7ad418b7525f76fa442f8511ec12f6d9 (diff) | |
drm/tidss: dispc: Switch VP_REG_FLD_MOD to using a mask
The VP_REG_FLD_MOD function takes the start and end bits as parameter
and will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change VP_REG_FLD_MOD to take the mask as an argument instead, and
let the caller create the mask. Eventually, this mask will be moved to a
define.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250827-drm-tidss-field-api-v3-12-7689b664cc63@kernel.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/tidss')
| -rw-r--r-- | drivers/gpu/drm/tidss/tidss_dispc.c | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 3d807b129c09..0255f7156f46 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -622,13 +622,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport) #define VP_REG_GET(dispc, vp, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx)))) -#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ +#define VP_REG_FLD_MOD(dispc, vp, idx, val, mask) \ ({ \ struct dispc_device *_dispc = (dispc); \ u32 _vp = (vp); \ u32 _idx = (idx); \ u32 _reg = dispc_vp_read(_dispc, _vp, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) @@ -1113,7 +1113,8 @@ static void dispc_set_num_datalines(struct dispc_device *dispc, v = 3; } - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, + GENMASK(10, 8)); } static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_videoport, @@ -1240,12 +1241,14 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, FIELD_PREP(GENMASK(11, 0), mode->crtc_hdisplay - 1) | FIELD_PREP(GENMASK(27, 16), mode->crtc_vdisplay - 1)); - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(0, 0)); } void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) @@ -1266,7 +1269,8 @@ bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(5, 5)); } enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; @@ -2440,7 +2444,7 @@ static void dispc_vp_init(struct dispc_device *dispc) /* Enable the gamma Shadow bit-field for all VPs*/ for (i = 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); } static void dispc_initial_config(struct dispc_device *dispc) @@ -2673,8 +2677,8 @@ static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, cprenable = 1; } - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - cprenable, 15, 15); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, + GENMASK(15, 15)); } static s16 dispc_S31_32_to_s3_8(s64 coef) @@ -2739,8 +2743,8 @@ static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, colorconvenable = 1; } - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - colorconvenable, 24, 24); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, + GENMASK(24, 24)); } static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, @@ -2891,7 +2895,8 @@ static void dispc_softreset_k2g(struct dispc_device *dispc) spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) - VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } static int dispc_softreset(struct dispc_device *dispc) |