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-rw-r--r--arch/arm64/Kconfig.platforms8
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/bst/Makefile2
-rw-r--r--arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts24
-rw-r--r--arch/arm64/boot/dts/bst/bstc1200.dtsi97
-rw-r--r--arch/arm64/configs/defconfig1
-rw-r--r--arch/riscv/Kconfig.socs13
-rw-r--r--arch/riscv/boot/dts/Makefile2
-rw-r--r--arch/riscv/boot/dts/anlogic/Makefile2
-rw-r--r--arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts28
-rw-r--r--arch/riscv/boot/dts/anlogic/dr1v90.dtsi100
-rw-r--r--arch/riscv/boot/dts/tenstorrent/Makefile2
-rw-r--r--arch/riscv/boot/dts/tenstorrent/blackhole-card.dts14
-rw-r--r--arch/riscv/boot/dts/tenstorrent/blackhole.dtsi108
-rw-r--r--arch/riscv/configs/defconfig2
15 files changed, 404 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 3dbff0261f0a..fff14807c965 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -119,6 +119,14 @@ config ARCH_BLAIZE
help
This enables support for the Blaize SoC family
+config ARCH_BST
+ bool "Black Sesame Technologies SoC Family"
+ help
+ This enables support for Black Sesame Technologies (BST) SoC family.
+ BST produces automotive-grade system-on-chips for intelligent driving,
+ focusing on computer vision and AI capabilities. The BST C1200 family
+ includes SoCs for ADAS and autonomous driving applications.
+
config ARCH_CIX
bool "Cixtech SoC family"
help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index b0844404eda1..98ec8f1b76e4 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
+subdir-y += bst
subdir-y += cavium
subdir-y += cix
subdir-y += exynos
diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
new file mode 100644
index 000000000000..4c1b8b4cdad8
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
new file mode 100644
index 000000000000..5eb9ef369d8c
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "bstc1200.dtsi"
+
+/ {
+ model = "BST C1200-96 CDCU1.0 4C2G";
+ compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@810000000 {
+ device_type = "memory";
+ reg = <0x8 0x10000000 0x0 0x30000000>,
+ <0x8 0xc0000000 0x1 0x0>,
+ <0xc 0x00000000 0x0 0x40000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
new file mode 100644
index 000000000000..dd13c6bfc3c8
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "bst,c1200";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ uart0: serial@20008000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ clock-frequency = <25000000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x32800000 0x0 0x10000>,
+ <0x0 0x32880000 0x0 0x100000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ always-on;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d6ff5e4cba6a..45288ec9eaf7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -47,6 +47,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_BST=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 848e7149e443..d621b85dd63b 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
+config ARCH_ANLOGIC
+ bool "Anlogic SoCs"
+ help
+ This enables support for Anlogic SoC platform hardware.
+
config ARCH_ESWIN
bool "ESWIN SoCs"
help
@@ -63,6 +68,14 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_TENSTORRENT
+ bool "Tenstorrent SoCs"
+ help
+ This enables support for Tenstorrent SoC platforms.
+ Current support is for Blackhole P100 and P150 PCIe cards.
+ The Blackhole SoC contains four RISC-V CPU tiles each
+ consisting of 4x SiFive X280 cores.
+
config ARCH_THEAD
bool "T-HEAD RISC-V SoCs"
depends on MMU && !XIP_KERNEL
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 3763d199c70a..69d8751fb17c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += andes
+subdir-y += anlogic
subdir-y += canaan
subdir-y += eswin
subdir-y += microchip
@@ -9,4 +10,5 @@ subdir-y += sifive
subdir-y += sophgo
subdir-y += spacemit
subdir-y += starfive
+subdir-y += tenstorrent
subdir-y += thead
diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile
new file mode 100644
index 000000000000..87f3b2f418cf
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
new file mode 100644
index 000000000000..597407655efd
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "dr1v90.dtsi"
+
+/ {
+ model = "Milianke MLKPAI-FS01";
+ compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
new file mode 100644
index 000000000000..a5d0765ade32
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Anlogic DR1V90";
+ compatible = "anlogic,dr1v90";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <800000000>;
+
+ cpu@0 {
+ compatible = "nuclei,ux900", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
+ "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
+ "zihintpause", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aclint_mswi: interrupt-controller@68031000 {
+ compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
+ reg = <0x0 0x68031000 0x0 0x4000>;
+ interrupts-extended = <&cpu0_intc 3>;
+ };
+
+ aclint_mtimer: timer@68035000 {
+ compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
+ reg = <0x0 0x68035000 0x0 0x8000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu0_intc 7>;
+ };
+
+ aclint_sswi: interrupt-controller@6803d000 {
+ compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
+ reg = <0x0 0x6803d000 0x0 0x3000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 1>;
+ };
+
+ plic: interrupt-controller@6c000000 {
+ compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x6c000000 0x0 0x4000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ riscv,ndev = <150>;
+ };
+
+ uart0: serial@f8400000 {
+ compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xf8400000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ interrupts = <71>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@f8401000 {
+ compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xf8401000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ interrupts = <72>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
new file mode 100644
index 000000000000..2c81faaba462
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts
new file mode 100644
index 000000000000..f53667ce73a9
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "blackhole.dtsi"
+
+/ {
+ model = "Tenstorrent Blackhole";
+ compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole";
+
+ memory@400030000000 {
+ device_type = "memory";
+ reg = <0x4000 0x30000000 0x1 0x00000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
new file mode 100644
index 000000000000..6408810d8d80
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright 2025 Tenstorrent AI ULC
+/dts-v1/;
+
+/ {
+ compatible = "tenstorrent,blackhole";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <50000000>;
+
+ cpu@0 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ mmu-type = "riscv,sv57";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ mmu-type = "riscv,sv57";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ mmu-type = "riscv,sv57";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@3 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ mmu-type = "riscv,sv57";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ clint0: timer@2000000 {
+ compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
+ <&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
+ <&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
+ <&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
+ };
+
+ plic0: interrupt-controller@c000000 {
+ compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x0c000000 0x0 0x04000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <128>;
+ };
+ };
+};
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 48afe30d42e8..cd736a1d657e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -23,12 +23,14 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_ARCH_ANDES=y
+CONFIG_ARCH_ANLOGIC=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
CONFIG_ARCH_SPACEMIT=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_TENSTORRENT=y
CONFIG_ARCH_THEAD=y
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_CANAAN=y
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-08 23:23:08 +0000