| Age | Commit message (Expand) | Author |
|---|---|---|
| 2025-11-21 | cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent | Yushan Wang |
| 2025-11-21 | cache: Make top level Kconfig menu a boolean dependent on RISCV | Jonathan Cameron |
| 2024-08-01 | cache: StarFive: Require a 64-bit system | Palmer Dabbelt |
| 2024-05-28 | cache: Add StarFive StarLink cache management | Joshua Yeong |
| 2023-11-22 | soc: sifive: shunt ccache driver to drivers/cache | Conor Dooley |
| 2023-10-26 | riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT | Christoph Hellwig |
| 2023-09-01 | cache: Add L2 cache management for Andes AX45MP RISC-V core | Lad Prabhakar |