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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
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2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()Ville Syrjälä
Use intel_de_wait_for_{set,clear}_ms() instead of intel_de_wait_ms() where appropriate. Done with cocci (with manual formatting fixes): @@ identifier func !~ "intel_de_wait_for"; expression display, reg, mask, timeout_ms; @@ func(...) { <... ( - intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL) + intel_de_wait_for_set_ms(display, reg, mask, timeout_ms) | - intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL) + intel_de_wait_for_clear_ms(display, reg, mask, timeout_ms) ) ...> } Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-11-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_us()Ville Syrjälä
Use intel_de_wait_for_{set,clear}_us() instead of intel_de_wait_us() where appropriate. Done with cocci (with manual formatting fixes): @@ identifier func !~ "intel_de_wait_for"; expression display, reg, mask, timeout_us; @@ func(...) { <... ( - intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL) + intel_de_wait_for_set_us(display, reg, mask, timeout_us) | - intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL) + intel_de_wait_for_clear_us(display, reg, mask, timeout_us) ) ...> } Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-10-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-11-11drm/i915/de: Use intel_de_wait_ms() for the obvious casesVille Syrjälä
Replace some users of intel_de_wait_custom() with intel_de_wait_ms(). This includes the cases where we pass in the default 2 microsecond fast timeout, which is also what intel_de_wait_ms() uses so there are no functional changes here. Done with cocci (with manual formatting fixes): @@ expression display, reg, mask, value, timeout_ms, out_value; @@ - intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value) + intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-7-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-11-11drm/i915/de: Use intel_de_wait_us()Ville Syrjälä
Convert some of the intel_de_wait_custom() users over to intel_de_wait_us(). We'll eventually want to eliminate intel_de_wait_custom() as it's a hinderance towards using poll_timeout_us(). This includes all the obvious cases where we only specify a microsecond timeout to intel_de_wait_custom(). Done with cocci (with manual formatting fixes): @@ expression display, reg, mask, value, timeout_us, out_value; @@ - intel_de_wait_custom(display, reg, mask, value, timeout_us, 0, out_value) + intel_de_wait_us(display, reg, mask, value, timeout_us, out_value) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-6-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-11-11drm/i915/de: Include units in intel_de_wait*() function namesVille Syrjälä
intel_de_wait*() take the timeout in milliseconds. Include that information in the function name to make life less confusing. I'll also be introducing microsecond variants of these later. Done with cocci: @@ @@ ( static int - intel_de_wait + intel_de_wait_ms (...) { ... } | static int - intel_de_wait_fw + intel_de_wait_fw_ms (...) { ... } | static int - intel_de_wait_for_set + intel_de_wait_for_set_ms (...) { ... } | static int - intel_de_wait_for_clear + intel_de_wait_for_clear_ms (...) { ... } ) @@ @@ ( - intel_de_wait + intel_de_wait_ms | - intel_de_wait_fw + intel_de_wait_fw_ms | - intel_de_wait_for_set + intel_de_wait_for_set_ms | - intel_de_wait_for_clear + intel_de_wait_for_clear_ms ) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-4-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-11-07drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_MS/Ville Syrjälä
Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT to make it match all its other counterparts. v2: It's _MS not _US (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251106155249.2810-1-ville.syrjala@linux.intel.com
2025-11-07drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/Ville Syrjälä
The slow vs. fast timeout stuff is really just an implementation detail. Let's not spread that terminology in random timeout defines. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251106152049.21115-7-ville.syrjala@linux.intel.com
2025-11-07drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_USVille Syrjälä
XELPDP_MSGBUS_TIMEOUT_FAST_US looks to be just an obfuscated version of the default 2 microsecond fast timeout used by intel_wait_for_register(). Get rid of it to make it clear what's going on here. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251106152049.21115-6-ville.syrjala@linux.intel.com
2025-11-07drm/i915/cx0: Replace XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US with ↵Ville Syrjälä
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS There was a completely unjustified change to the cx0 powerdown timeout, and the way it was done now prevents future conversion to poll_timeout_us(). Assuming there was some reason the bigger timeout let's nuke the old short timeout (XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US) nd replace it with the bigger timeout (XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS). For consistency with intel_wait_for_register() we'll stick to the default 2 usec for the fast timeout. v2: Go for the longer (ms) timeout in case it actually matters v3: Note the defaullt 2 usec fast timeout (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251106152049.21115-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-11-07drm/i915/cx0: Nuke extraneous timeout debugsVille Syrjälä
The actual timeout used isn't particularly interesting, so don't print it. Makes the code simpler. The debugs are also using some random capitalizaton rule. Clean that up a bit while at it. Also intel_cx0_powerdown_change_sequence() used one timeout in the actual code but printed a different one. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251106152049.21115-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal
Define function to verify the LT PHY PLL state function and call it in intel_modeset_verify_crtc. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-24-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal
Hook up the LT Phy enable and disable sequences using encoder-> enable/disable_clock and reusing the TBT enable disable sequence from cx0 PHY since it remains the same. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal
Program the rest of the LT Phy Non TBT PLL Enable sequence. This can be done in a single patch since the rest of the prequistie functions are already coded in. Bspec: 74492, 69701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal
Program the LT PHY P2P transaction which uses P2M cycle to get get data fro Phy when it is ready and then go read the MAC register from the MAC address space. Bspec: 68966, 74497, 74483, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal
Fetch the tables which need to be used and program it in the specified VDR register space. Everything is done over the respective lanes. Bspec: 68862, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal
Read PHY_VDR_0_CONFIG to check if there is any change in the register and decide based on that if P2P sequence to change the data rate of LT PHY are required or not. This scenario only happens if the requested mode uses 1.62Gbps with DP mode since LT PHY defaults to this mode if any other mode is requested we need to follow the whole sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal
Add a wrapper on cx0 powerdown change sequence for LT Phy usage, as the sequence remains unchanged when going from SNPS Phy to LT Phy. Bspec: 74495 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal
Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and make it non static. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal
Define function to bring phy lane out of reset for LT Phy and the corresponding pre-requisite steps before we follow the steps for Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence function in which we can place this function Bspec: 77449, 74749, 74499, 74495, 68960 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal
Change the register bit naming for powerdown values from CX0 to XELPDP so that it can be used with LT Phy too. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-3-suraj.kandpal@intel.com
2025-10-31drm/i915/display: switch to intel_display_utils.hJani Nikula
The remaining utils display needs from i915_utils.h are primarily MISSING_CASE() and fetch_and_zero(), with a couple of i915_inject_probe_failure() uses. To avoid excessive churn, add duplicates of MISSING_CASE() and fetch_and_zero() to intel_display_utils.h, and switch display to use the display utils. As long as there are display files that include i915_drv.h, which includes i915_utils.h, we'll need #ifndef guards for MISSING_CASE() and fetch_and_zero() in both utils headers. We can remove them once display no longer depends on i915_drv.h. A couple of files in display still need i915_utils.h for i915_inject_probe_failure(). Annotate this. They will be handled separately. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/79f9e31ca64c8c045834d48e20ceb0c515d1e9e1.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-16drm/i915/display: Add missing clock to C10 PHY state compute/HW readoutImre Deak
Clock value is missing from C10 hw readout stage. Let's fix this. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-8-mika.kahola@intel.com
2025-10-16drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programmingImre Deak
The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are not specified as a must-be-zero field. Accordingly this reserved field shouldn't be zeroed; to ensure that use an RMW to update the PHY_C20_HDMI_RATE field (which is bits 1:0 of the register). Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-7-mika.kahola@intel.com
2025-10-16drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programmingImre Deak
Make sure all the DP/HDMI/HDMI-FRL flags are programmed in all the modes the PLL is configured. Atm the DP mode flag is not programmed in case the PLL is configured for HDMI mode for instance. This is incorrect after HW reset, since the DP mode flag is asserted after reset, hence would need to be cleared for HDMI, but also incorrect because of the same reason after configuring the PLL to HDMI mode after it was used in DP mode (for instance on a DP++ connector). There is a similar issue with the HDMI-FRL flag, potentially remaining set when configuring the PLL in DP mode. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-6-mika.kahola@intel.com
2025-10-16drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL flag macroImre Deak
Define PHY_C20_IS_HDMI_FRL, so it can be used instead of the plain bit number. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-5-mika.kahola@intel.com
2025-10-16drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE ↵Imre Deak
flag macro Move the PHY_C20_CONTEXT_TOGGLE flag's definition under the register containing the flag and refer to the flag always by its name instead of a plain bit number. v2: Amend commit log to match what the patch does. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-4-mika.kahola@intel.com
2025-10-16drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macroImre Deak
Define PHY_C20_IS_DP, so it can be used instead of the plain bit number. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-3-mika.kahola@intel.com
2025-10-16drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macrosImre Deak
Rename the PHY_C20_CUSTOM_SERDES / PHY_C20_CUSTOM_SERDES_MASK register field names to PHY_C20_DP_RATE / PHY_C20_DP_RATE_MASK, and move the definitions under the actual register containing the fields. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-2-mika.kahola@intel.com
2025-09-23drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY ADnyaneshwar Bhadane
On PTL, no combo PHY is connected to PORT B. However, PORT B can still be used for Type-C and will utilize the C20 PHY for eDP over Type-C. In such configurations, VBTs also enumerate PORT B. This leads to issues where PORT B is incorrectly identified as using the C10 PHY, due to the assumption that returning true for PORT B in intel_encoder_is_c10phy() would not cause problems. From PTL's perspective, only PORT A/PHY A uses the C10 PHY. Update the helper intel_encoder_is_c10phy() to return true only for PORT A/PHY on PTL. v2: Change the condition code style for ptl/wcl Bspec: 72571,73944 Fixes: 9d10de78a37f ("drm/i915/wcl: C10 phy connected to port A and B") Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250922150317.2334680-4-dnyaneshwar.bhadane@intel.com
2025-07-23drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg readJouni Högander
According to C10 VDR Register programming sequence we need set C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from MsgBus. v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes Bspec: 68962 Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending") Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
2025-07-23drm/i915/display: Ensure phy is accessible on lfps configurationJouni Högander
Ensure phy is accessible on lfps configuration by adding intel_cx0_phy_transaction_begin/end around it. Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending") Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250722125618.1842615-4-jouni.hogander@intel.com
2025-07-23drm/i915/display: Avoid unnecessarily calling intel_cx0_get_owned_lane_maskJouni Högander
Currently we are always calling intel_cx0_get_owned_lane_mask when intel_lnl_mac_transmit_lfps is called. Avoid this in cases where it's not needed. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250722125618.1842615-3-jouni.hogander@intel.com
2025-07-23drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPMJouni Högander
We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries" since we started configuring LFPS sending. According to Bspec Configuring LFPS sending is needed only when using AUXLess ALPM. This patch avoids these failures by configuring LFPS sending only when using AUXLess ALPM. Bspec: 68849 Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250722125618.1842615-2-jouni.hogander@intel.com
2025-06-18drm/i915/wcl: C10 phy connected to port A and BDnyaneshwar Bhadane
WCL added a c10 phy connected to port B. PTL code is currently restricting c10 to phy_a only. PTL doesn't have a PHY connected to PORT B; as such,there will never be a case where PTL uses PHY B. WCL uses PORT A and B with the C10 PHY.Reusing the condition for WCL and extending it for PORT B should not cause any issues for PTL. -v2: Reuse and extend PTL condition for WCL (Matt) Bspec: 73944 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20250613193146.3549862-9-dnyaneshwar.bhadane@intel.com
2025-06-11drm/i915/display: drop i915_reg.h include where possibleJani Nikula
A number of files have unnecessary i915_reg.h includes. Drop them. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/7c4002322f4d8132fd2eaa1a4d688539cdd043c3.1749469962.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-29drm/i915/display: Add function to configure LFPS sendingJouni Högander
Add function to configre LFPS sending for Panel Replay according to link training sequence in HAS document. This assumes we are using AUX Less always if it's supported by the sink and the source. v2: - drop HAS reference - replay kerneldoc comment with a generic comment - check display version in intel_lnl_mac_transmit_lfps Bspec: 68849 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-11-jouni.hogander@intel.com
2025-05-29drm/i915/alpm: Move port alpm configurationJouni Högander
It is specified in Bspec where port alpm configuration is supposed to be performed. Change accordingly. v2: - drop HAS reference - ensure PORT_ALPM registers are not writen on older platform Bspec: 68849 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-9-jouni.hogander@intel.com
2025-05-14drm/i915/ptl: Use everywhere the correct DDI port clock select maskImre Deak
The PTL XELPDP_PORT_CLOCK_CTL register XELPDP_DDI_CLOCK_SELECT field's size is 5 bits vs. the earlier platforms where its size is 4 bits. Make sure the field is read-out/programmed everywhere correctly, according to the above. Cc: Mika Kahola <mika.kahola@intel.com> Cc: stable@vger.kernel.org # v6.13+ Tested-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250512142600.824347-1-imre.deak@intel.com
2025-04-22drm/i915/display: drop lots of unnecessary #include i915_drv.hJani Nikula
With the PCH macros switched to use struct intel_display, we have a number of files that no longer need struct drm_i915_private or anything else from i915_drv.h anymore. Remove the #include, and add the missing includes that were previously implicit. v2: Drop even more of the includes Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/5dc9e6a98461c344febac4c645875d8688eba906.1744880985.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-02-19drm/i915/display: Allow display PHYs to reset power stateMika Kahola
The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated PHY is not being brought up shortly, use these steps to move the PHY to the lowest power state to save power. 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz. This brings lanes out of reset and enables the PLL to allow powerdown to be moved to the Disable state. 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL. v2: Rename WA function to more descriptive (Jani) For PTL, only port A needs this wa Add helpers to check presence of C10 phy and pll enabling (Imre) v3: Rename wa function (Imre) Check return value of C10 pll tables readout (Imre) Use PLL request to check pll enabling (Imre) v4: Move intel_cx0_pll_is_enabled() right after intel_cx0_pll_disable() (Imre) Add drm_WARN_ON() if C10 state cannot be calculated from the tables (Imre) v5: Add debug message on PLL enabling (Imre) Add check for intel_encoder_is_dig_port() (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250218100019.740556-3-mika.kahola@intel.com
2025-02-19drm/i915/display: Drop crtc_state from C10/C20 pll programmingMika Kahola
For PLL programming for C10 and C20 we don't need to carry crtc_state but instead use only necessary parts of the crtc_state i.e. pll_state. This change is needed to PTL wa 14023648281 where we would need to otherwise pass an artificial crtc_state with majority of the struct members initialized as NULL. v2: Use err instead of val for error handling (Imre) Unify parameter order (Imre) v3: Fix misplaced port_clock, and is_dp in intel_c20_pll_program() call (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250218100019.740556-2-mika.kahola@intel.com
2025-02-10drm/i915: Convert intel_display_power_{get,put}*() to intel_displayVille Syrjälä
Pass intel_display to the display power stuff. These are spread all over the place so tend to hinder clean conversions of whole files. TODO: The gt part/unpark power domain shenanigans need some kind of more abstract interface... v2: Deal with cmtg Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250206185533.32306-7-ville.syrjala@linux.intel.com
2025-02-05drm/i915/cx0: convert to struct intel_display based platform checksJani Nikula
Switch the IS_<PLATFORM>() checks to display->platform.<platform>, and drop a number of struct drm_i915_private pointers in the process. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250204134228.2934744-3-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-02-05Merge drm/drm-next into drm-intel-nextJani Nikula
Sync with v6.14-rc1. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-01-24drm/i915/cx0: Set ssc_enabled for c20 tooSuraj Kandpal
ssc_enabled does not get set for c20 phy. We makes sure we set ssc_enabled for both c10 and c20. Bspec: 74491 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250122053022.1544881-1-suraj.kandpal@intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20250122053022.1544881-1-suraj.kandpal@intel.com
2025-01-23drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHYAnkit Nautiyal
Try HDMI PLL alogorithm for C10 PHY, if there are no pre-computed tables. Also get rid of the helpers to get rate for HDMI for C10/20 PHY, as we no longer depend only on pre-computed tables. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250120042122.1029481-6-ankit.k.nautiyal@intel.com
2025-01-16drm/i915/cx0_phy: Update HDMI TMDS C20 algorithm valueDnyaneshwar Bhadane
In the C20 algorithm for HDMI TMDS, certain fields have been updated in the BSpec to set values for SRAM_GENERIC_<A/B>_TX_CNTX_CFG_1, such as tx_misc and dac_ctrl_range for Xe2LPD, Xe2HPD and MTL/ARL. This patch covers fields that need to be set based on the platform type. Some ARLs SoCs cannot be directly distinguished by their GMD version Id, Specifically to set value of tx_misc, so PCI Host Bridge IDs are used for differentiation. v2: - Relocate defines and Restructure the code(Jani) v3: - Replace conditions with display.platform.<platform> (jani) - Move host bridge check to new function (Jani) v4: - Identify/Replace arrowlake_u as meteorlake_u(Jani) Bspec:74165,74491 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217201301.3593054-3-dnyaneshwar.bhadane@intel.com
2025-01-10Merge tag 'drm-intel-next-2025-01-07' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Driver Changes: - Some DG2 refactor to fix DG2 bugs when operating with certain CPUs (Raag) - Use hw support for min/interim ddb allocation for async flip (Vinod) - More general code refactor to allow full display separation (Jani) - Expose dsc sink max slice count via debugfs (Swati) - Fix C10 pll programming sequence (Suraj) - Fix DG1 power gate sequence (Rodrigo) - Use preemption timeout on selftest cleanup (Janusz) - DP DSC related fixes (Ankit) - Fix HDCP compliance test (Suraj) - Clean and Optimise mtl_ddi_prepare_link_retrain (Suraj) - Adjust Added Wake Time with PKG_C_LATENCY (Animesh) - Enabling uncompressed 128b/132b UHBR SST (Jani) - Handle hdmi connector init failures, and no HDMI/DP cases (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Z31_WPbBoHkwgEA9@intel.com
2025-01-09Merge tag 'drm-xe-next-2025-01-07' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - OA new property: 'unblock after N reports' (Ashutosh) i915 display Changes: - UHBR rates for Thunderbolt (Kahola) Driver Changes: - IRQ related fixes and improvements (Ilia) - Revert some changes that break a mesa debug tool (John) - Fix migration issues (Nirmoy) - Enable GuC's WA_DUAL_QUEUE for newer platforms (Daniele) - Move shrink test out of xe_bo (Nirmoy) - SRIOV PF: Use correct function to check LMEM provisioning (Michal) - Fix a false-positive "Missing outer runtime PM protection" warning (Rodrigo) - Make GSCCS disabling message less alarming (Daniele) - Fix DG1 power gate sequence (Rodrigo) - Xe files fixes (Lucas) - Fix a potential TP_printk UAF (Thomas) - OA Fixes (Umesh) - Fix tlb invalidation when wedging (Lucas) - Documentation fix (Lucas) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Z31579j3V3XCPFaK@intel.com
2024-12-19drm/i915/display: UHBR rates for ThunderboltMika Kahola
tbt-alt mode is missing uhbr rates 10G and 20G. This requires requires pll clock rates 312.5 MHz and 625 MHz to be added, respectively. The uhbr rates are supported only form PTL+ platforms. v2: Add drm_WARN_ON() to check if port clock is not supported by the platform (Imre) Combine forward ungate with mask parameter (Imre) Rename XE3LPDP_* to XE3D_* (Imre) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217143440.572308-1-mika.kahola@intel.com
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-11 07:35:32 +0000