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path: root/drivers/gpu/drm/amd/display/dc/inc
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8 daysMerge tag 'amd-drm-next-6.19-2025-12-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-12-02: amdgpu: - Unified MES fix - SMU 11 unbalanced irq fix - Fix for driver reloading on APUs - pp_table sysfs fix - Fix memory leak in fence handling - HDMI fix - DC cursor fixes - eDP panel parsing fix - Brightness fix - DC analog fixes - EDID retry fixes - UserQ fixes - RAS fixes - IP discovery fix - Add missing locking in amdgpu_ttm_access_memory_sdma() - Smart Power OLED fix - PRT and page fault fixes for GC 6-8 - VMID reservation fix - ACP platform device fix - Add missing vm fault handling for GC 11-12 - VPE fix amdkfd: - Partitioning fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251202220101.2039347-1-alexander.deucher@amd.com
2025-11-21Merge tag 'v6.18-rc6' into drm-nextDave Airlie
Linux 6.18-rc6 Backmerge in order to merge msm next Signed-off-by: Dave Airlie <airlied@redhat.com>
2025-11-18drm/amd/display: Add pipe topology history to dcNicholas Carbones
[Why] There is no way to check pipe topology update history through a dump. [How] Add a topology history structure to dc with snapshots of the most recent pipe topology updates. Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Nicholas Carbones <ncarbone@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: dynamically clock gate before and after prefetchLeo Chen
[Why] An invalidation request arriving during prefetch can potentially hang the system if dynamic clock gating is enabled and memory power requests are disabled. [How] • Disable clock gating and enable memory power requests for the duration of the prefetch. • Turn on clock gating and disable memory power requests again after prefetch is complete. Limit the scope for DCN35 and DCN42 only. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: To support Replay frame skip modeChuntao Tso
[Why & How] The change is to optimize the Replay power saving by reducing the refresh rate with frame skipping mode Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Chuntao Tso <chunttso@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-28drm/amd/display: Add concept of analog encoders (v2)Timur Kristóf
Add a num_analog_stream_encoders field to indicate how many analog stream encoders are present. When analog stream encoders are present, create them. Additionally, add an analog_engine field to link encoders and search for supported analog encoders in the BIOS for each link. When connecting an RGB signal, search for analog stream encoders. The actual DCE analog link and stream encoder is going to be added in a subsequent commit. v2: Add check to see if an analog engine is really supported. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-28drm/amd/display: Introduce MAX_LINK_ENCODERS (v2)Timur Kristóf
We are going to support analog encoders as well, not just digital, so we need to make space for them in various arrays. v2: Fix typo. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-28drm/amd/display: Add more DC HW state info to underflow loggingKaren Chen
[Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Karen Chen <Karen.Chen@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-28drm/amd/display: Rename dml2 to dml2_0 folderAustin Zheng
[Why] dml2 folder contains all logic for all versions of DML2 This is currently DML2.0 and DML2.1. Rename dml2 to dml2_0 folder to reflect this better (dml2_0 for DML2.0). [How] Rename dml2 to dml2_0 folder and update dml2 references to use dml2_0 folder. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: waynelin <Wayne.Lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-21drm/amd/display: increase max link count and fix link->enc NULL pointer accessCharlene Liu
[why] 1.) dc->links[MAX_LINKS] array size smaller than actual requested. max_connector + max_dpia + 4 virtual = 14. increase from 12 to 14. 2.) hw_init() access null LINK_ENC for dpia non display_endpoint. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit d7f5a61e1b04ed87b008c8d327649d184dc5bb45) Cc: stable@vger.kernel.org
2025-10-20drm/amd/display: update perfmon measurement interfacesWenjing Liu
[how] The commit update interfaces for dchubbub perfmon meansurement to better reflect our requirements. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-20drm/amd/display: Update spacing in structAlvin Lee
Update spacing so that fields with longer name will still be aligned correctly (new fields to be added). Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-20drm/amd/display: Update DCN401 path for cursor offloadAlvin Lee
[Description] The DCN401 cursor offload path needs to take into account use_mall_for_cursor, and also need to ensure the dcn32 function assigns the cursor cache fields (DCN401 uses the dcn32 implementation). Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-20drm/amd/display: increase max link count and fix link->enc NULL pointer accessCharlene Liu
[why] 1.) dc->links[MAX_LINKS] array size smaller than actual requested. max_connector + max_dpia + 4 virtual = 14. increase from 12 to 14. 2.) hw_init() access null LINK_ENC for dpia non display_endpoint. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-13drm/amd/display: Driver implementation for cursor offloading to DMUNicholas Kazlauskas
[Why] We require an interlock between driver and firmware for upcoming features and given that this could possibly happen on any single cursor programming call (and that we can't asynchronously wait for firmware to respond because of it) we'd be regressing cursor performance by at least an extra 40us per call. When we could possibly have cursor update every 20us - 100s from high frequency gaming mice this means that we'd be stuttering or dropping updates and impacting overall cursor performance. We want a solution that can: 1. Interlock between other firmware features 2. Not stall out or require the DMCUB lock for every single update [How] When cursor offloading is enabled and supported by an ASIC driver will route the cursor programming through to DMU as part of the regular DC stream cursor programming interfaces for attributes and position. The atomic pipe programming version will not be updated: this will still follow the existing programming path by keeping track of a field that specifies when the register writes should be deferred to DMU. Cursor locking is not required when cursor offload is in progress since the updates are consolidated and processed by DMU once at the end of the frame in a periodic manner. The shared buffer the firmware queries from is allocated along with the rest of the scratch state region in an area that's accessible by both firmware and driver. The size of the cursor offload (v1) state will not change, but it does have a unique union per ASIC version with room for expansion if needed. When firmware features notifying DMU of DRR updates are not enabled we now send an explicit vtotal min/max update via driver to DMU firmware whenever the vtotal max changes. This is to allow the cursor programming to determine the appropriate latch update point offset from vupdate. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15Revert "drm/amd/display: Reduce Stack Usage by moving 'audio_output' into ↵Martin Leung
'stream_res' v4" This reverts commit 1cf1205ef268 ("drm/amd/display: Reduce Stack Usage by moving 'audio_output' into 'stream_res' v4") Reason for revert: Causes DP compliance errors Acked-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/display: Add DSC padding for OVT SupportRelja Vojvodic
[Why] -Certain OVT timings require DSC configurations which divide the horizontal active unevenly across DSC slices -DSC slices must be even, so padding needs to be added to the active to make this possible -The pixel clock of the HW now needs to be increased to accommodate the extra padded pixels -To keep the line time the same, the blank of the HW timing needs to be increased as well [How] -Calculate h_active padding, h_total padding, and pixel clock based off of the original OVT timing and DSC calculations -Store these values in the pipe and program HW with these modifications -Added general support for cases where DSC slice config does not evenly split the horizontal active by fixing some slice width calculations -Updated PPS calculations for these cases Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Relja Vojvodic <rvojvodi@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/display: Rename header file link.h to link_service.hWesley Chalmers
[WHY] Header file name "link.h" collides with system header when dc is compiled as a user-mode library [WHAT] Rename link.h to link_service.h to avoid name collision Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/display: prepare dml 2.1 for new asicDmytro Laktyushkin
[Why&How] prepare dml 2.1 for new asic Acked-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-05drm/amd/display: Correct sequences and delays for DCN35 PG & RCGOvidiu Bunea
[why] The current PG & RCG programming in driver has some gaps and incorrect sequences. [how] Added delays after ungating clocks to allow ramp up, increased polling to allow more time for power up, and removed the incorrect sequences. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-05drm/amd/display: Update dchubbub.h for hubbub perfmon supportWenjing Liu
[why] dchubbub supports performance monitoring for hubbub. The interfaces define the performance monitoring events and their attributes. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-29drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PGIvan Lipski
[Why&How] ON DCN314, clearing DPP SW structure without power gating it can cause a double cursor in full screen with non-native scaling. A W/A that clears CURSOR0_CONTROL cursor_enable flag if dcn10_plane_atomic_power_down is called and DPP power gating is disabled. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168 Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-29drm/amd/display: Add Component To Handle Bounding Box Values and IP CapsAustin Zheng
[Why] Bounding box values can be stored in multiple locations. (e.g. PMFW, VBIOS, DMUB). The source and interpretation of these values can vary with DCN revision so there should be a component that can gather these values and translate them accordingly [How] Have component start with the statically defined values as a base. Then update them as needed with DCN-specific logic Guard this component with FPU flags since values need to be in float point. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-27drm/amd/display: wait for otg update pending latch before clock optimizationYihan Zhu
[WHY & HOW] OTG pending update unlatched will cause system fail, wait OTG fully disabled to avoid this error. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-27drm/amd/display: Add control flags to force PSR / replayKarthi Kandasamy
To change PSR/Replay behavior based on OS preferences, add some config options. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-18drm/amd/display: Delete unused functionsClay King
[WHAT] Removing unused code Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-04drm/amd/display: Adding interface to log hw state when underflow happensMuhammad Ahmed
[why] Will help us better debug underflow issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Muhammad Ahmed <Muhammad.Ahmed@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-04drm/amd/display: Fixing hubp programming of 3dlut fast loadReza Amini
[why] HUBP needs to know the size of the lut's destination in MPC. This is currently defaulted to 17, and needs to be set for specific lut size. [how] Define and apply the missing hubp field. Taking this opportunity to consolidate the programming of 3dlut into a hubp and mpc function. Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by: Reza Amini <reza.amini@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-28drm/amd/display: Add eDP AUXless ALPMDuncan Ma
[Why & How] Add AUX-less ALPM capability check and initialization Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Duncan Ma <Duncan.Ma@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-28drm/amd/display: Add comma to last entry of enum for consistencyAlvin Lee
[Why&How] Add comma to last entry of enum for consistency. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-28drm/amd/display: Reduce Stack Usage by moving 'audio_output' into ↵Srinivasan Shanmugam
'stream_res' v4 The function `dp_retrain_link_dp_test` currently allocates a large audio_output array on the stack, causing the stack frame size to exceed the compiler limit (1080 bytes > 1024 bytes). This change prevents stack overflow issues: amdgpu/../display/dc/link/accessories/link_dp_cts.c:65:13: warning: stack frame size (1080) exceeds limit (1024) in 'dp_retrain_link_dp_test' [-Wframe-larger-than] static void dp_retrain_link_dp_test(struct dc_link *link, v2: Move audio-related data like `audio_output` is kept "per pipe" to manage the audio for that specific display pipeline/display output path (stream). (Wenjing) v3: Update in all the places where `build_audio_output` is currently called with a separate audio_output variable on the stack & wherever `audio_output` is passed to other functions `dce110_apply_single_controller_ctx_to_hw()` & `dce110_setup_audio_dto()` (like `az_configure`, `wall_dto_setup`) replace with usage of `pipe_ctx->stream_res.audio_output` to centralize audio data per pipe. v4: Remove empty lines before `build_audio_output`. (Alex) Fixes: 9c6669c2e21a ("drm/amd/display: Fix Link Override Sequencing When Switching Between DIO/HPO") Cc: Wayne Lin <wayne.lin@amd.com> Cc: George Shen <george.shen@amd.com> Cc: Michael Strauss <michael.strauss@amd.com> Cc: Alvin Lee <Alvin.Lee2@amd.com> Cc: Ray Wu <ray.wu@amd.com> Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-15drm/amd/display: Initial support for SmartMuxAurabindo Pillai
SmartMux is a mechanism to switch the GPU being used for scanout in a hybrid configuration. This is used for devices with an eDP and two GPUs. This is only valid when the system has a physical switch (Multiplexer) in the board to switch between the two GPUs. When a graphically intensive workload like a game is being run, the system can be switch the active display to the dGPU, so that we can avoid copying the buffer from dGPU to APU for scanout. This helps with latency and FPS. When power consumption is preferred, the system can be switched to the APU. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-15drm/amd/display: Add static pg implementations for future useLeo Chen
[Why & How] Add static pg implementations and debug flags for future use. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-15drm/amd/display: Refactor DSC cap calculationsDillon Varone
[WHY] DSC block level should only be responsible for reporting single DSC instance capabilities. Factoring in ODM combine requirements should be handled in dc_dsc.c. Both components should acquire clocks from clk_mgr to determine throughput capabilities instead of relying on hard coded values as these can differ by SoC and SKU. [HOW] 1) Add dsc_get_single_enc_caps to acquire single DSC instance capabilities (replacing dsc_get_enc_caps), factoring in DSCCLK 2) add build_dsc_enc_caps to combine single DSC instance capabilities 3) account for max pixel rate per pipe (DISPCLK) when calculating minimum slice count Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-07-15drm/amd/display: MPC basic allocation logic and TMZYihan Zhu
[WHY & HOW] Adding basic logic to allocate unused RMCM block and TMZ support. Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-30drm/amd/display: Fix Link Override Sequencing When Switching Between DIO/HPOMichael Strauss
[WHY] When performing certain link maintenance compliance tests or forcing link settings, changing between 128b/132b and 8b/10b rates no longer works on some ASICs. Some rate divider updates only occur when we set timings or validate state, which is not performed currently when toggling DPMS to change rates. [HOW] Re-calculate dividers and reprogram audio when switching between DIO and HPO through DP compliance/escape code path. Add OTG disable/re-enable so we don't touch the clock while OTG is active. Acquire dcLock before forcing link settings to avoid thread synchronization errors due to added programming in escape code path and potential HPD interrupts. Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Mike Katsnelson <mike.katsnelson@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-30drm/amd/display: Remove unused tunnel BW validationCruise Hung
[Why & How] The tunnel BW validation code has changed to the new one. Remove the unused code. The DP tunneling overhead is not updated in SST. Move updating DP tunneling overhead for both SST and MST. Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-24drm/amd/display: Add num_slices_h to set_dto_dscclk signatureIlya Bakoulin
Add the number of horizontal slices argument to allow configuring clock based on slice number. Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-24drm/amd/display: Add new DP tunnel bandwidth validationCruise Hung
[Why & How] Add new function for DP tunnel bandwidth validation. It uses the estimated BW and allocated BW to validate the timings. Reviewed-by: PeiChen Huang <peichen.huang@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-18drm/amd/display: add APG struct to stream_enc for future useCharlene Liu
some new asics will have an APG instance taking over certain functions. Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-18drm/amd/display: Fix kernel docs for new struct membersAlex Hung
[WHAT & HOW] Add kernel-doc for new struct members for lut3d_caps and mpc_funcs. This fixes the follow warnings from "make htmldocs". ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1106: warning: Function parameter or struct member 'mcm' not described in 'mpc_funcs' ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1106: warning: Function parameter or struct member 'rmcm' not described in 'mpc_funcs' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'mcm_3d_lut_caps' not described in 'mpc_color_caps' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'rmcm_3d_lut_caps' not described in 'mpc_color_caps' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'preblend' not described in 'mpc_color_caps' Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-18drm/amd/display: Add RMCM debug loggingYihan Zhu
[WHY & HOW] Add new FL feature debug logging into the existing DTN logging. Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-18drm/amd/display: Refactor DML2 DC power instanceDillon Varone
[WHY & HOW] Use a dedicated DC power option and instance pair. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-03drm/amd/display: replace fast_validate with enum dc_validate_modeYan Li
[Why] The boolean fast_validate is used as an input parameter in multiple functions. To support more scenarios, we are replacing it with enum dc_validate_mode. [How] The enum dc_validate_mode introduces three possible values: 1) DC_VALIDATE_MODE_AND_PROGRAMMING: Apply the mode to hardware 2) DC_VALIDATE_MODE_ONLY: Check whether the mode can be supported 3) DC_VALIDATE_MODE_AND_STATE_INDEX: Check if the mode can be supported, and determine the optimal voltage level needed to support it. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Yan Li <yan.li@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-06-03drm/amd/display: Add DML path for FAMS methodsOleh Kuzhylnyi
[Why] DML needs a path for FAMS methods. [How] Apply instance of fams2_stream_sub_params_v2 structure with a FAMS placeholder for DML. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Oleh Kuzhylnyi <okuzhyln@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-16drm/amd/display: Move mcache allocation programming from DML to resourceKarthi Kandasamy
[Why] mcache allocation programming is not part of DML's core responsibilities. Keeping this logic in DML leads to poor separation of concerns and complicates maintenance. [How] Refactored code to move mcache parameter preparation and mcache ID assignment into the resource file. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-16drm/amd/display: Support external tunneling featureCruise Hung
[Why & How] The original code only supports the tunneling for embedded one. To support external tunneling feature, it needs to check Tunneling_Support bit register. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-05drm/amd/display: Refactor SubVP cursor limiting logicDillon Varone
[WHY] There are several gaps that can result in SubVP being enabled with incompatible HW cursor sizes, and unjust restrictions to cursor size due to wrong predictions on future usage of SubVP. [HOW] - remove "prediction" logic in favor of tagging based on previous SubVP usage - block SubVP if current HW cursor settings are incompatible - provide interface for DM to determine if HW cursor should be disabled due to an attempt to enable SubVP Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-05Revert "drm/amd/display: Refactor SubVP cursor limiting logic"Ryan Seto
This reverts commit 19e743f0fb73 ("drm/amd/display: Refactor SubVP cursor limiting logic") Reason for revert: Corruption Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-04-22drm/amd/display: Refactor SubVP cursor limiting logicDillon Varone
[WHY] There are several gaps that can result in SubVP being enabled with incompatible HW cursor sizes, and unjust restrictions to cursor size due to wrong predictions on future usage of SubVP [HOW] - remove "prediction" logic in favor of tagging based on previous SubVP usage - block SubVP if current HW cursor settings are incompatible - provide interface for DM to determine if HW cursor should be disabled due to an attempt to enable SubVP Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Mark Broadworth <mark.broadworth@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-10 12:22:45 +0000